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72 lines
1003 B
72 lines
1003 B
// SPDX-License-Identifier: (GPL-2.0 OR MIT) |
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/* Copyright (c) 2020 Microchip Technology Inc */ |
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/dts-v1/; |
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#include "microchip-mpfs.dtsi" |
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/* Clock frequency (in Hz) of the rtcclk */ |
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#define RTCCLK_FREQ 1000000 |
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/ { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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model = "Microchip PolarFire-SoC Icicle Kit"; |
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compatible = "microchip,mpfs-icicle-kit"; |
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chosen { |
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stdout-path = &serial0; |
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}; |
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cpus { |
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timebase-frequency = <RTCCLK_FREQ>; |
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}; |
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memory@80000000 { |
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device_type = "memory"; |
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reg = <0x0 0x80000000 0x0 0x40000000>; |
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clocks = <&clkcfg 26>; |
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}; |
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soc { |
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}; |
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}; |
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&serial0 { |
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status = "okay"; |
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}; |
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&serial1 { |
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status = "okay"; |
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}; |
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&serial2 { |
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status = "okay"; |
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}; |
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&serial3 { |
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status = "okay"; |
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}; |
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&sdcard { |
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status = "okay"; |
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}; |
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&emac0 { |
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phy-mode = "sgmii"; |
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phy-handle = <&phy0>; |
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phy0: ethernet-phy@8 { |
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reg = <8>; |
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ti,fifo-depth = <0x01>; |
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}; |
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}; |
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&emac1 { |
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status = "okay"; |
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phy-mode = "sgmii"; |
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phy-handle = <&phy1>; |
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phy1: ethernet-phy@9 { |
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reg = <9>; |
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ti,fifo-depth = <0x01>; |
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}; |
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};
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