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378 lines
8.3 KiB
378 lines
8.3 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) |
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*/ |
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#ifndef _ASM_BITOPS_H |
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#define _ASM_BITOPS_H |
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#ifndef _LINUX_BITOPS_H |
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#error only <linux/bitops.h> can be included directly |
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#endif |
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#ifndef __ASSEMBLY__ |
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#include <linux/types.h> |
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#include <linux/compiler.h> |
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#include <asm/barrier.h> |
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#ifndef CONFIG_ARC_HAS_LLSC |
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#include <asm/smp.h> |
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#endif |
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#ifdef CONFIG_ARC_HAS_LLSC |
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/* |
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* Hardware assisted Atomic-R-M-W |
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*/ |
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#define BIT_OP(op, c_op, asm_op) \ |
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static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\ |
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{ \ |
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unsigned int temp; \ |
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\ |
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m += nr >> 5; \ |
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\ |
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nr &= 0x1f; \ |
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\ |
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__asm__ __volatile__( \ |
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"1: llock %0, [%1] \n" \ |
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" " #asm_op " %0, %0, %2 \n" \ |
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" scond %0, [%1] \n" \ |
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" bnz 1b \n" \ |
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: "=&r"(temp) /* Early clobber, to prevent reg reuse */ \ |
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: "r"(m), /* Not "m": llock only supports reg direct addr mode */ \ |
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"ir"(nr) \ |
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: "cc"); \ |
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} |
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/* |
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* Semantically: |
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* Test the bit |
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* if clear |
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* set it and return 0 (old value) |
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* else |
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* return 1 (old value). |
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* |
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* Since ARC lacks a equivalent h/w primitive, the bit is set unconditionally |
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* and the old value of bit is returned |
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*/ |
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#define TEST_N_BIT_OP(op, c_op, asm_op) \ |
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static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\ |
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{ \ |
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unsigned long old, temp; \ |
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\ |
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m += nr >> 5; \ |
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\ |
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nr &= 0x1f; \ |
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\ |
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/* \ |
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* Explicit full memory barrier needed before/after as \ |
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* LLOCK/SCOND themselves don't provide any such smenatic \ |
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*/ \ |
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smp_mb(); \ |
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\ |
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__asm__ __volatile__( \ |
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"1: llock %0, [%2] \n" \ |
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" " #asm_op " %1, %0, %3 \n" \ |
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" scond %1, [%2] \n" \ |
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" bnz 1b \n" \ |
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: "=&r"(old), "=&r"(temp) \ |
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: "r"(m), "ir"(nr) \ |
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: "cc"); \ |
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\ |
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smp_mb(); \ |
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\ |
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return (old & (1 << nr)) != 0; \ |
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} |
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#else /* !CONFIG_ARC_HAS_LLSC */ |
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/* |
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* Non hardware assisted Atomic-R-M-W |
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* Locking would change to irq-disabling only (UP) and spinlocks (SMP) |
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* |
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* There's "significant" micro-optimization in writing our own variants of |
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* bitops (over generic variants) |
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* |
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* (1) The generic APIs have "signed" @nr while we have it "unsigned" |
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* This avoids extra code to be generated for pointer arithmatic, since |
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* is "not sure" that index is NOT -ve |
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* (2) Utilize the fact that ARCompact bit fidding insn (BSET/BCLR/ASL) etc |
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* only consider bottom 5 bits of @nr, so NO need to mask them off. |
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* (GCC Quirk: however for constant @nr we still need to do the masking |
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* at compile time) |
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*/ |
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#define BIT_OP(op, c_op, asm_op) \ |
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static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\ |
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{ \ |
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unsigned long temp, flags; \ |
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m += nr >> 5; \ |
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\ |
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/* \ |
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* spin lock/unlock provide the needed smp_mb() before/after \ |
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*/ \ |
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bitops_lock(flags); \ |
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\ |
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temp = *m; \ |
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*m = temp c_op (1UL << (nr & 0x1f)); \ |
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\ |
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bitops_unlock(flags); \ |
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} |
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#define TEST_N_BIT_OP(op, c_op, asm_op) \ |
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static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\ |
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{ \ |
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unsigned long old, flags; \ |
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m += nr >> 5; \ |
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\ |
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bitops_lock(flags); \ |
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\ |
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old = *m; \ |
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*m = old c_op (1UL << (nr & 0x1f)); \ |
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\ |
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bitops_unlock(flags); \ |
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\ |
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return (old & (1UL << (nr & 0x1f))) != 0; \ |
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} |
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#endif |
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/*************************************** |
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* Non atomic variants |
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**************************************/ |
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#define __BIT_OP(op, c_op, asm_op) \ |
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static inline void __##op##_bit(unsigned long nr, volatile unsigned long *m) \ |
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{ \ |
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unsigned long temp; \ |
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m += nr >> 5; \ |
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\ |
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temp = *m; \ |
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*m = temp c_op (1UL << (nr & 0x1f)); \ |
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} |
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#define __TEST_N_BIT_OP(op, c_op, asm_op) \ |
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static inline int __test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\ |
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{ \ |
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unsigned long old; \ |
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m += nr >> 5; \ |
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\ |
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old = *m; \ |
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*m = old c_op (1UL << (nr & 0x1f)); \ |
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\ |
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return (old & (1UL << (nr & 0x1f))) != 0; \ |
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} |
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#define BIT_OPS(op, c_op, asm_op) \ |
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\ |
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/* set_bit(), clear_bit(), change_bit() */ \ |
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BIT_OP(op, c_op, asm_op) \ |
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\ |
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/* test_and_set_bit(), test_and_clear_bit(), test_and_change_bit() */\ |
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TEST_N_BIT_OP(op, c_op, asm_op) \ |
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\ |
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/* __set_bit(), __clear_bit(), __change_bit() */ \ |
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__BIT_OP(op, c_op, asm_op) \ |
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\ |
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/* __test_and_set_bit(), __test_and_clear_bit(), __test_and_change_bit() */\ |
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__TEST_N_BIT_OP(op, c_op, asm_op) |
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BIT_OPS(set, |, bset) |
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BIT_OPS(clear, & ~, bclr) |
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BIT_OPS(change, ^, bxor) |
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/* |
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* This routine doesn't need to be atomic. |
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*/ |
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static inline int |
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test_bit(unsigned int nr, const volatile unsigned long *addr) |
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{ |
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unsigned long mask; |
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addr += nr >> 5; |
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mask = 1UL << (nr & 0x1f); |
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return ((mask & *addr) != 0); |
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} |
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#ifdef CONFIG_ISA_ARCOMPACT |
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/* |
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* Count the number of zeros, starting from MSB |
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* Helper for fls( ) friends |
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* This is a pure count, so (1-32) or (0-31) doesn't apply |
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* It could be 0 to 32, based on num of 0's in there |
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* clz(0x8000_0000) = 0, clz(0xFFFF_FFFF)=0, clz(0) = 32, clz(1) = 31 |
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*/ |
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static inline __attribute__ ((const)) int clz(unsigned int x) |
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{ |
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unsigned int res; |
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__asm__ __volatile__( |
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" norm.f %0, %1 \n" |
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" mov.n %0, 0 \n" |
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" add.p %0, %0, 1 \n" |
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: "=r"(res) |
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: "r"(x) |
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: "cc"); |
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return res; |
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} |
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static inline int constant_fls(unsigned int x) |
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{ |
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int r = 32; |
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if (!x) |
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return 0; |
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if (!(x & 0xffff0000u)) { |
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x <<= 16; |
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r -= 16; |
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} |
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if (!(x & 0xff000000u)) { |
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x <<= 8; |
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r -= 8; |
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} |
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if (!(x & 0xf0000000u)) { |
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x <<= 4; |
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r -= 4; |
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} |
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if (!(x & 0xc0000000u)) { |
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x <<= 2; |
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r -= 2; |
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} |
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if (!(x & 0x80000000u)) |
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r -= 1; |
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return r; |
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} |
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/* |
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* fls = Find Last Set in word |
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* @result: [1-32] |
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* fls(1) = 1, fls(0x80000000) = 32, fls(0) = 0 |
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*/ |
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static inline __attribute__ ((const)) int fls(unsigned int x) |
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{ |
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if (__builtin_constant_p(x)) |
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return constant_fls(x); |
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return 32 - clz(x); |
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} |
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/* |
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* __fls: Similar to fls, but zero based (0-31) |
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*/ |
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static inline __attribute__ ((const)) int __fls(unsigned long x) |
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{ |
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if (!x) |
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return 0; |
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else |
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return fls(x) - 1; |
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} |
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/* |
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* ffs = Find First Set in word (LSB to MSB) |
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* @result: [1-32], 0 if all 0's |
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*/ |
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#define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); }) |
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/* |
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* __ffs: Similar to ffs, but zero based (0-31) |
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*/ |
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static inline __attribute__ ((const)) unsigned long __ffs(unsigned long word) |
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{ |
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if (!word) |
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return word; |
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return ffs(word) - 1; |
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} |
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#else /* CONFIG_ISA_ARCV2 */ |
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/* |
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* fls = Find Last Set in word |
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* @result: [1-32] |
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* fls(1) = 1, fls(0x80000000) = 32, fls(0) = 0 |
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*/ |
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static inline __attribute__ ((const)) int fls(unsigned long x) |
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{ |
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int n; |
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asm volatile( |
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" fls.f %0, %1 \n" /* 0:31; 0(Z) if src 0 */ |
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" add.nz %0, %0, 1 \n" /* 0:31 -> 1:32 */ |
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: "=r"(n) /* Early clobber not needed */ |
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: "r"(x) |
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: "cc"); |
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return n; |
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} |
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/* |
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* __fls: Similar to fls, but zero based (0-31). Also 0 if no bit set |
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*/ |
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static inline __attribute__ ((const)) int __fls(unsigned long x) |
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{ |
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/* FLS insn has exactly same semantics as the API */ |
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return __builtin_arc_fls(x); |
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} |
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/* |
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* ffs = Find First Set in word (LSB to MSB) |
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* @result: [1-32], 0 if all 0's |
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*/ |
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static inline __attribute__ ((const)) int ffs(unsigned long x) |
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{ |
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int n; |
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asm volatile( |
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" ffs.f %0, %1 \n" /* 0:31; 31(Z) if src 0 */ |
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" add.nz %0, %0, 1 \n" /* 0:31 -> 1:32 */ |
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" mov.z %0, 0 \n" /* 31(Z)-> 0 */ |
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: "=r"(n) /* Early clobber not needed */ |
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: "r"(x) |
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: "cc"); |
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return n; |
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} |
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/* |
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* __ffs: Similar to ffs, but zero based (0-31) |
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*/ |
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static inline __attribute__ ((const)) unsigned long __ffs(unsigned long x) |
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{ |
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unsigned long n; |
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asm volatile( |
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" ffs.f %0, %1 \n" /* 0:31; 31(Z) if src 0 */ |
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" mov.z %0, 0 \n" /* 31(Z)-> 0 */ |
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: "=r"(n) |
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: "r"(x) |
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: "cc"); |
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return n; |
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} |
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#endif /* CONFIG_ISA_ARCOMPACT */ |
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/* |
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* ffz = Find First Zero in word. |
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* @return:[0-31], 32 if all 1's |
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*/ |
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#define ffz(x) __ffs(~(x)) |
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#include <asm-generic/bitops/hweight.h> |
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#include <asm-generic/bitops/fls64.h> |
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#include <asm-generic/bitops/sched.h> |
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#include <asm-generic/bitops/lock.h> |
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#include <asm-generic/bitops/find.h> |
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#include <asm-generic/bitops/le.h> |
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#include <asm-generic/bitops/ext2-atomic-setbit.h> |
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#endif /* !__ASSEMBLY__ */ |
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#endif
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