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226 lines
5.0 KiB
226 lines
5.0 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Common time service routines for LoongArch machines. |
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* |
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited |
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*/ |
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#include <linux/clockchips.h> |
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#include <linux/delay.h> |
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#include <linux/export.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/kernel.h> |
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#include <linux/sched_clock.h> |
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#include <linux/spinlock.h> |
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#include <asm/cpu-features.h> |
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#include <asm/loongarch.h> |
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#include <asm/time.h> |
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u64 cpu_clock_freq; |
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EXPORT_SYMBOL(cpu_clock_freq); |
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u64 const_clock_freq; |
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EXPORT_SYMBOL(const_clock_freq); |
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static DEFINE_RAW_SPINLOCK(state_lock); |
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static DEFINE_PER_CPU(struct clock_event_device, constant_clockevent_device); |
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static void constant_event_handler(struct clock_event_device *dev) |
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{ |
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} |
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irqreturn_t constant_timer_interrupt(int irq, void *data) |
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{ |
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int cpu = smp_processor_id(); |
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struct clock_event_device *cd; |
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/* Clear Timer Interrupt */ |
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write_csr_tintclear(CSR_TINTCLR_TI); |
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cd = &per_cpu(constant_clockevent_device, cpu); |
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cd->event_handler(cd); |
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return IRQ_HANDLED; |
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} |
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static int constant_set_state_oneshot(struct clock_event_device *evt) |
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{ |
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unsigned long timer_config; |
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raw_spin_lock(&state_lock); |
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timer_config = csr_read64(LOONGARCH_CSR_TCFG); |
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timer_config |= CSR_TCFG_EN; |
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timer_config &= ~CSR_TCFG_PERIOD; |
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csr_write64(timer_config, LOONGARCH_CSR_TCFG); |
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raw_spin_unlock(&state_lock); |
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return 0; |
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} |
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static int constant_set_state_oneshot_stopped(struct clock_event_device *evt) |
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{ |
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unsigned long timer_config; |
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raw_spin_lock(&state_lock); |
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timer_config = csr_read64(LOONGARCH_CSR_TCFG); |
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timer_config &= ~CSR_TCFG_EN; |
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csr_write64(timer_config, LOONGARCH_CSR_TCFG); |
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raw_spin_unlock(&state_lock); |
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return 0; |
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} |
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static int constant_set_state_periodic(struct clock_event_device *evt) |
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{ |
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unsigned long period; |
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unsigned long timer_config; |
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raw_spin_lock(&state_lock); |
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period = const_clock_freq / HZ; |
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timer_config = period & CSR_TCFG_VAL; |
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timer_config |= (CSR_TCFG_PERIOD | CSR_TCFG_EN); |
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csr_write64(timer_config, LOONGARCH_CSR_TCFG); |
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raw_spin_unlock(&state_lock); |
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return 0; |
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} |
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static int constant_set_state_shutdown(struct clock_event_device *evt) |
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{ |
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return 0; |
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} |
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static int constant_timer_next_event(unsigned long delta, struct clock_event_device *evt) |
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{ |
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unsigned long timer_config; |
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delta &= CSR_TCFG_VAL; |
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timer_config = delta | CSR_TCFG_EN; |
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csr_write64(timer_config, LOONGARCH_CSR_TCFG); |
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return 0; |
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} |
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static unsigned long __init get_loops_per_jiffy(void) |
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{ |
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unsigned long lpj = (unsigned long)const_clock_freq; |
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do_div(lpj, HZ); |
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return lpj; |
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} |
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static long init_timeval; |
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void sync_counter(void) |
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{ |
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/* Ensure counter begin at 0 */ |
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csr_write64(-init_timeval, LOONGARCH_CSR_CNTC); |
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} |
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static int get_timer_irq(void) |
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{ |
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struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY); |
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if (d) |
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return irq_create_mapping(d, EXCCODE_TIMER - EXCCODE_INT_START); |
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return -EINVAL; |
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} |
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int constant_clockevent_init(void) |
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{ |
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int irq; |
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unsigned int cpu = smp_processor_id(); |
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unsigned long min_delta = 0x600; |
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unsigned long max_delta = (1UL << 48) - 1; |
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struct clock_event_device *cd; |
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static int timer_irq_installed = 0; |
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irq = get_timer_irq(); |
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if (irq < 0) |
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pr_err("Failed to map irq %d (timer)\n", irq); |
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cd = &per_cpu(constant_clockevent_device, cpu); |
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cd->name = "Constant"; |
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cd->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_PERCPU; |
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cd->irq = irq; |
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cd->rating = 320; |
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cd->cpumask = cpumask_of(cpu); |
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cd->set_state_oneshot = constant_set_state_oneshot; |
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cd->set_state_oneshot_stopped = constant_set_state_oneshot_stopped; |
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cd->set_state_periodic = constant_set_state_periodic; |
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cd->set_state_shutdown = constant_set_state_shutdown; |
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cd->set_next_event = constant_timer_next_event; |
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cd->event_handler = constant_event_handler; |
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clockevents_config_and_register(cd, const_clock_freq, min_delta, max_delta); |
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if (timer_irq_installed) |
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return 0; |
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timer_irq_installed = 1; |
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sync_counter(); |
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if (request_irq(irq, constant_timer_interrupt, IRQF_PERCPU | IRQF_TIMER, "timer", NULL)) |
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pr_err("Failed to request irq %d (timer)\n", irq); |
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lpj_fine = get_loops_per_jiffy(); |
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pr_info("Constant clock event device register\n"); |
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return 0; |
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} |
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static u64 read_const_counter(struct clocksource *clk) |
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{ |
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return drdtime(); |
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} |
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static u64 native_sched_clock(void) |
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{ |
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return read_const_counter(NULL); |
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} |
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static struct clocksource clocksource_const = { |
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.name = "Constant", |
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.rating = 400, |
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.read = read_const_counter, |
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.mask = CLOCKSOURCE_MASK(64), |
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.flags = CLOCK_SOURCE_IS_CONTINUOUS, |
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.vdso_clock_mode = VDSO_CLOCKMODE_CPU, |
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}; |
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int __init constant_clocksource_init(void) |
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{ |
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int res; |
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unsigned long freq = const_clock_freq; |
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res = clocksource_register_hz(&clocksource_const, freq); |
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sched_clock_register(native_sched_clock, 64, freq); |
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pr_info("Constant clock source device register\n"); |
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return res; |
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} |
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void __init time_init(void) |
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{ |
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if (!cpu_has_cpucfg) |
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const_clock_freq = cpu_clock_freq; |
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else |
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const_clock_freq = calc_const_freq(); |
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init_timeval = drdtime() - csr_read64(LOONGARCH_CSR_CNTC); |
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constant_clockevent_init(); |
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constant_clocksource_init(); |
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}
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