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407 lines
9.9 KiB
407 lines
9.9 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* pxa2xx-i2s.c -- ALSA Soc Audio Layer |
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* |
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* Copyright 2005 Wolfson Microelectronics PLC. |
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* Author: Liam Girdwood |
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* [email protected] |
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*/ |
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/device.h> |
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#include <linux/delay.h> |
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#include <linux/clk.h> |
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#include <linux/platform_device.h> |
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#include <linux/io.h> |
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#include <sound/core.h> |
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#include <sound/pcm.h> |
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#include <sound/initval.h> |
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#include <sound/soc.h> |
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#include <sound/pxa2xx-lib.h> |
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#include <sound/dmaengine_pcm.h> |
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#include <mach/hardware.h> |
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#include <mach/audio.h> |
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#include "pxa2xx-i2s.h" |
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/* |
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* I2S Controller Register and Bit Definitions |
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*/ |
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#define SACR0 __REG(0x40400000) /* Global Control Register */ |
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#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */ |
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#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ |
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#define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */ |
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#define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */ |
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#define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */ |
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#define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */ |
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#define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */ |
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#define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */ |
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#define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */ |
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#define SACR0_EFWR (1 << 4) /* Enable EFWR Function */ |
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#define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */ |
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#define SACR0_BCKD (1 << 2) /* Bit Clock Direction */ |
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#define SACR0_ENB (1 << 0) /* Enable I2S Link */ |
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#define SACR1_ENLBF (1 << 5) /* Enable Loopback */ |
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#define SACR1_DRPL (1 << 4) /* Disable Replaying Function */ |
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#define SACR1_DREC (1 << 3) /* Disable Recording Function */ |
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#define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */ |
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#define SASR0_I2SOFF (1 << 7) /* Controller Status */ |
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#define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */ |
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#define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */ |
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#define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */ |
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#define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */ |
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#define SASR0_BSY (1 << 2) /* I2S Busy */ |
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#define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */ |
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#define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */ |
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#define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */ |
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#define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */ |
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#define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */ |
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#define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */ |
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#define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */ |
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#define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */ |
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struct pxa_i2s_port { |
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u32 sadiv; |
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u32 sacr0; |
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u32 sacr1; |
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u32 saimr; |
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int master; |
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u32 fmt; |
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}; |
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static struct pxa_i2s_port pxa_i2s; |
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static struct clk *clk_i2s; |
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static int clk_ena = 0; |
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static struct snd_dmaengine_dai_dma_data pxa2xx_i2s_pcm_stereo_out = { |
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.addr = __PREG(SADR), |
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.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, |
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.chan_name = "tx", |
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.maxburst = 32, |
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}; |
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static struct snd_dmaengine_dai_dma_data pxa2xx_i2s_pcm_stereo_in = { |
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.addr = __PREG(SADR), |
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.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, |
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.chan_name = "rx", |
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.maxburst = 32, |
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}; |
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static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); |
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struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); |
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if (IS_ERR(clk_i2s)) |
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return PTR_ERR(clk_i2s); |
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if (!snd_soc_dai_active(cpu_dai)) |
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SACR0 = 0; |
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return 0; |
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} |
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/* wait for I2S controller to be ready */ |
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static int pxa_i2s_wait(void) |
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{ |
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int i; |
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/* flush the Rx FIFO */ |
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for (i = 0; i < 16; i++) |
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SADR; |
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return 0; |
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} |
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static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
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unsigned int fmt) |
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{ |
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/* interface format */ |
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_I2S: |
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pxa_i2s.fmt = 0; |
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break; |
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case SND_SOC_DAIFMT_LEFT_J: |
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pxa_i2s.fmt = SACR1_AMSL; |
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break; |
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} |
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
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case SND_SOC_DAIFMT_CBS_CFS: |
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pxa_i2s.master = 1; |
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break; |
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case SND_SOC_DAIFMT_CBM_CFS: |
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pxa_i2s.master = 0; |
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break; |
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default: |
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break; |
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} |
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return 0; |
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} |
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static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai, |
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int clk_id, unsigned int freq, int dir) |
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{ |
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if (clk_id != PXA2XX_I2S_SYSCLK) |
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return -ENODEV; |
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return 0; |
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} |
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static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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struct snd_dmaengine_dai_dma_data *dma_data; |
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if (WARN_ON(IS_ERR(clk_i2s))) |
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return -EINVAL; |
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clk_prepare_enable(clk_i2s); |
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clk_ena = 1; |
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pxa_i2s_wait(); |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
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dma_data = &pxa2xx_i2s_pcm_stereo_out; |
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else |
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dma_data = &pxa2xx_i2s_pcm_stereo_in; |
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snd_soc_dai_set_dma_data(dai, substream, dma_data); |
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/* is port used by another stream */ |
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if (!(SACR0 & SACR0_ENB)) { |
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SACR0 = 0; |
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if (pxa_i2s.master) |
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SACR0 |= SACR0_BCKD; |
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SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1); |
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SACR1 |= pxa_i2s.fmt; |
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} |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
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SAIMR |= SAIMR_TFS; |
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else |
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SAIMR |= SAIMR_RFS; |
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switch (params_rate(params)) { |
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case 8000: |
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SADIV = 0x48; |
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break; |
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case 11025: |
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SADIV = 0x34; |
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break; |
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case 16000: |
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SADIV = 0x24; |
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break; |
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case 22050: |
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SADIV = 0x1a; |
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break; |
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case 44100: |
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SADIV = 0xd; |
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break; |
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case 48000: |
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SADIV = 0xc; |
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break; |
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case 96000: /* not in manual and possibly slightly inaccurate */ |
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SADIV = 0x6; |
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break; |
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} |
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return 0; |
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} |
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static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
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struct snd_soc_dai *dai) |
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{ |
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int ret = 0; |
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
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SACR1 &= ~SACR1_DRPL; |
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else |
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SACR1 &= ~SACR1_DREC; |
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SACR0 |= SACR0_ENB; |
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break; |
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case SNDRV_PCM_TRIGGER_RESUME: |
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
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case SNDRV_PCM_TRIGGER_STOP: |
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case SNDRV_PCM_TRIGGER_SUSPEND: |
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
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break; |
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default: |
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ret = -EINVAL; |
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} |
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return ret; |
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} |
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static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
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SACR1 |= SACR1_DRPL; |
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SAIMR &= ~SAIMR_TFS; |
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} else { |
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SACR1 |= SACR1_DREC; |
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SAIMR &= ~SAIMR_RFS; |
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} |
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if ((SACR1 & (SACR1_DREC | SACR1_DRPL)) == (SACR1_DREC | SACR1_DRPL)) { |
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SACR0 &= ~SACR0_ENB; |
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pxa_i2s_wait(); |
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if (clk_ena) { |
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clk_disable_unprepare(clk_i2s); |
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clk_ena = 0; |
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} |
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} |
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} |
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#ifdef CONFIG_PM |
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static int pxa2xx_soc_pcm_suspend(struct snd_soc_component *component) |
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{ |
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/* store registers */ |
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pxa_i2s.sacr0 = SACR0; |
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pxa_i2s.sacr1 = SACR1; |
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pxa_i2s.saimr = SAIMR; |
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pxa_i2s.sadiv = SADIV; |
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/* deactivate link */ |
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SACR0 &= ~SACR0_ENB; |
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pxa_i2s_wait(); |
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return 0; |
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} |
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static int pxa2xx_soc_pcm_resume(struct snd_soc_component *component) |
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{ |
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pxa_i2s_wait(); |
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SACR0 = pxa_i2s.sacr0 & ~SACR0_ENB; |
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SACR1 = pxa_i2s.sacr1; |
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SAIMR = pxa_i2s.saimr; |
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SADIV = pxa_i2s.sadiv; |
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SACR0 = pxa_i2s.sacr0; |
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return 0; |
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} |
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#else |
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#define pxa2xx_soc_pcm_suspend NULL |
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#define pxa2xx_soc_pcm_resume NULL |
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#endif |
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static int pxa2xx_i2s_probe(struct snd_soc_dai *dai) |
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{ |
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clk_i2s = clk_get(dai->dev, "I2SCLK"); |
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if (IS_ERR(clk_i2s)) |
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return PTR_ERR(clk_i2s); |
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/* |
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* PXA Developer's Manual: |
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* If SACR0[ENB] is toggled in the middle of a normal operation, |
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* the SACR0[RST] bit must also be set and cleared to reset all |
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* I2S controller registers. |
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*/ |
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SACR0 = SACR0_RST; |
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SACR0 = 0; |
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/* Make sure RPL and REC are disabled */ |
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SACR1 = SACR1_DRPL | SACR1_DREC; |
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/* Along with FIFO servicing */ |
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SAIMR &= ~(SAIMR_RFS | SAIMR_TFS); |
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snd_soc_dai_init_dma_data(dai, &pxa2xx_i2s_pcm_stereo_out, |
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&pxa2xx_i2s_pcm_stereo_in); |
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return 0; |
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} |
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static int pxa2xx_i2s_remove(struct snd_soc_dai *dai) |
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{ |
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clk_put(clk_i2s); |
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clk_i2s = ERR_PTR(-ENOENT); |
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return 0; |
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} |
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#define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ |
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SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ |
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SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000) |
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static const struct snd_soc_dai_ops pxa_i2s_dai_ops = { |
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.startup = pxa2xx_i2s_startup, |
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.shutdown = pxa2xx_i2s_shutdown, |
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.trigger = pxa2xx_i2s_trigger, |
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.hw_params = pxa2xx_i2s_hw_params, |
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.set_fmt = pxa2xx_i2s_set_dai_fmt, |
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.set_sysclk = pxa2xx_i2s_set_dai_sysclk, |
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}; |
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static struct snd_soc_dai_driver pxa_i2s_dai = { |
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.probe = pxa2xx_i2s_probe, |
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.remove = pxa2xx_i2s_remove, |
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.playback = { |
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.channels_min = 2, |
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.channels_max = 2, |
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.rates = PXA2XX_I2S_RATES, |
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.formats = SNDRV_PCM_FMTBIT_S16_LE,}, |
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.capture = { |
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.channels_min = 2, |
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.channels_max = 2, |
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.rates = PXA2XX_I2S_RATES, |
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.formats = SNDRV_PCM_FMTBIT_S16_LE,}, |
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.ops = &pxa_i2s_dai_ops, |
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.symmetric_rate = 1, |
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}; |
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static const struct snd_soc_component_driver pxa_i2s_component = { |
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.name = "pxa-i2s", |
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.pcm_construct = pxa2xx_soc_pcm_new, |
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.pcm_destruct = pxa2xx_soc_pcm_free, |
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.open = pxa2xx_soc_pcm_open, |
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.close = pxa2xx_soc_pcm_close, |
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.hw_params = pxa2xx_soc_pcm_hw_params, |
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.hw_free = pxa2xx_soc_pcm_hw_free, |
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.prepare = pxa2xx_soc_pcm_prepare, |
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.trigger = pxa2xx_soc_pcm_trigger, |
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.pointer = pxa2xx_soc_pcm_pointer, |
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.mmap = pxa2xx_soc_pcm_mmap, |
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.suspend = pxa2xx_soc_pcm_suspend, |
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.resume = pxa2xx_soc_pcm_resume, |
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}; |
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static int pxa2xx_i2s_drv_probe(struct platform_device *pdev) |
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{ |
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return devm_snd_soc_register_component(&pdev->dev, &pxa_i2s_component, |
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&pxa_i2s_dai, 1); |
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} |
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static struct platform_driver pxa2xx_i2s_driver = { |
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.probe = pxa2xx_i2s_drv_probe, |
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.driver = { |
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.name = "pxa2xx-i2s", |
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}, |
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}; |
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static int __init pxa2xx_i2s_init(void) |
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{ |
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clk_i2s = ERR_PTR(-ENOENT); |
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return platform_driver_register(&pxa2xx_i2s_driver); |
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} |
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static void __exit pxa2xx_i2s_exit(void) |
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{ |
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platform_driver_unregister(&pxa2xx_i2s_driver); |
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} |
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module_init(pxa2xx_i2s_init); |
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module_exit(pxa2xx_i2s_exit); |
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/* Module information */ |
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MODULE_AUTHOR("Liam Girdwood, [email protected]"); |
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MODULE_DESCRIPTION("pxa2xx I2S SoC Interface"); |
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MODULE_LICENSE("GPL"); |
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MODULE_ALIAS("platform:pxa2xx-i2s");
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