forked from Qortal/Brooklyn
187 lines
6.5 KiB
Systemverilog
187 lines
6.5 KiB
Systemverilog
//-----------------------------------------------------------------------------
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// The confidential and proprietary information contained in this file may
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// only be used by a person authorised under and to the extent permitted
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// by a subsisting licensing agreement from ARM Limited or its affiliates.
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//
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// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
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// ALL RIGHTS RESERVED
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//
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// This entire notice must be reproduced on all copies of this file
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// and copies of this file may only be made by a person if such person is
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// permitted to do so under the terms of a subsisting license agreement
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// from ARM Limited or its affiliates.
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//
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// Release Information : HERCULESAE-MP106-r0p1-00eac0
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//
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//-----------------------------------------------------------------------------
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// SystemVerilog (IEEE Std 1800-2012)
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//-----------------------------------------------------------------------------
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`include "herculesae_header.sv"
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module herculesae_vx_aesmc
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(
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input wire [127:0] d_in,
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output wire [127:0] mc
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);
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wire [7:0] i00;
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wire [7:0] i01;
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wire [7:0] i02;
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wire [7:0] i03;
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wire [7:0] i10;
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wire [7:0] i11;
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wire [7:0] i12;
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wire [7:0] i13;
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wire [7:0] i20;
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wire [7:0] i21;
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wire [7:0] i22;
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wire [7:0] i23;
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wire [7:0] i30;
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wire [7:0] i31;
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wire [7:0] i32;
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wire [7:0] i33;
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wire [7:0] s00;
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wire [7:0] s01;
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wire [7:0] s02;
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wire [7:0] s03;
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wire [7:0] s10;
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wire [7:0] s11;
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wire [7:0] s12;
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wire [7:0] s13;
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wire [7:0] s20;
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wire [7:0] s21;
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wire [7:0] s22;
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wire [7:0] s23;
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wire [7:0] s30;
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wire [7:0] s31;
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wire [7:0] s32;
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wire [7:0] s33;
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assign i33[7:0] = d_in[127:120];
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assign i23[7:0] = d_in[119:112];
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assign i13[7:0] = d_in[111:104];
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assign i03[7:0] = d_in[103:96];
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assign i32[7:0] = d_in[95:88];
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assign i22[7:0] = d_in[87:80];
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assign i12[7:0] = d_in[79:72];
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assign i02[7:0] = d_in[71:64];
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assign i31[7:0] = d_in[63:56];
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assign i21[7:0] = d_in[55:48];
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assign i11[7:0] = d_in[47:40];
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assign i01[7:0] = d_in[39:32];
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assign i30[7:0] = d_in[31:24];
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assign i20[7:0] = d_in[23:16];
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assign i10[7:0] = d_in[15:8];
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assign i00[7:0] = d_in[7:0];
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assign s00[7:0] = {i00[6:0],1'b0} ^ ({8{i00[7]}} & 8'h1b)
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^ {i10[6:0],1'b0} ^ ({8{i10[7]}} & 8'h1b) ^ i10[7:0]
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^ i20[7:0]
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^ i30[7:0];
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assign s01[7:0] = {i01[6:0],1'b0} ^ ({8{i01[7]}} & 8'h1b)
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^ {i11[6:0],1'b0} ^ ({8{i11[7]}} & 8'h1b) ^ i11[7:0]
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^ i21[7:0]
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^ i31[7:0];
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assign s02[7:0] = {i02[6:0],1'b0} ^ ({8{i02[7]}} & 8'h1b)
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^ {i12[6:0],1'b0} ^ ({8{i12[7]}} & 8'h1b) ^ i12[7:0]
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^ i22[7:0]
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^ i32[7:0];
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assign s03[7:0] = {i03[6:0],1'b0} ^ ({8{i03[7]}} & 8'h1b)
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^ {i13[6:0],1'b0} ^ ({8{i13[7]}} & 8'h1b) ^ i13[7:0]
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^ i23[7:0]
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^ i33[7:0];
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assign s10[7:0] = i00[7:0]
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^ {i10[6:0],1'b0} ^ ({8{i10[7]}} & 8'h1b)
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^ {i20[6:0],1'b0} ^ ({8{i20[7]}} & 8'h1b) ^ i20[7:0]
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^ i30[7:0];
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assign s11[7:0] = i01[7:0]
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^ {i11[6:0],1'b0} ^ ({8{i11[7]}} & 8'h1b)
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^ {i21[6:0],1'b0} ^ ({8{i21[7]}} & 8'h1b) ^ i21[7:0]
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^ i31[7:0];
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assign s12[7:0] = i02[7:0]
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^ {i12[6:0],1'b0} ^ ({8{i12[7]}} & 8'h1b)
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^ {i22[6:0],1'b0} ^ ({8{i22[7]}} & 8'h1b) ^ i22[7:0]
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^ i32[7:0];
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assign s13[7:0] = i03[7:0]
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^ {i13[6:0],1'b0} ^ ({8{i13[7]}} & 8'h1b)
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^ {i23[6:0],1'b0} ^ ({8{i23[7]}} & 8'h1b) ^ i23[7:0]
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^ i33[7:0];
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assign s20[7:0] = i00[7:0]
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^ i10[7:0]
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^ {i20[6:0],1'b0} ^ ({8{i20[7]}} & 8'h1b)
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^ {i30[6:0],1'b0} ^ ({8{i30[7]}} & 8'h1b) ^ i30[7:0];
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assign s21[7:0] = i01[7:0]
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^ i11[7:0]
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^ {i21[6:0],1'b0} ^ ({8{i21[7]}} & 8'h1b)
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^ {i31[6:0],1'b0} ^ ({8{i31[7]}} & 8'h1b) ^ i31[7:0];
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assign s22[7:0] = i02[7:0]
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^ i12[7:0]
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^ {i22[6:0],1'b0} ^ ({8{i22[7]}} & 8'h1b)
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^ {i32[6:0],1'b0} ^ ({8{i32[7]}} & 8'h1b) ^ i32[7:0];
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assign s23[7:0] = i03[7:0]
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^ i13[7:0]
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^ {i23[6:0],1'b0} ^ ({8{i23[7]}} & 8'h1b)
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^ {i33[6:0],1'b0} ^ ({8{i33[7]}} & 8'h1b) ^ i33[7:0];
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assign s30[7:0] = {i00[6:0],1'b0} ^ ({8{i00[7]}} & 8'h1b) ^ i00[7:0]
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^ i10[7:0]
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^ i20[7:0]
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^ {i30[6:0],1'b0} ^ ({8{i30[7]}} & 8'h1b);
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assign s31[7:0] = {i01[6:0],1'b0} ^ ({8{i01[7]}} & 8'h1b) ^ i01[7:0]
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^ i11[7:0]
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^ i21[7:0]
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^ {i31[6:0],1'b0} ^ ({8{i31[7]}} & 8'h1b);
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assign s32[7:0] = {i02[6:0],1'b0} ^ ({8{i02[7]}} & 8'h1b) ^ i02[7:0]
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^ i12[7:0]
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^ i22[7:0]
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^ {i32[6:0],1'b0} ^ ({8{i32[7]}} & 8'h1b);
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assign s33[7:0] = {i03[6:0],1'b0} ^ ({8{i03[7]}} & 8'h1b) ^ i03[7:0]
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^ i13[7:0]
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^ i23[7:0]
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^ {i33[6:0],1'b0} ^ ({8{i33[7]}} & 8'h1b);
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assign mc[127:120] = s33[7:0];
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assign mc[119:112] = s23[7:0];
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assign mc[111:104] = s13[7:0];
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assign mc[103:96] = s03[7:0];
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assign mc[95:88] = s32[7:0];
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assign mc[87:80] = s22[7:0];
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assign mc[79:72] = s12[7:0];
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assign mc[71:64] = s02[7:0];
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assign mc[63:56] = s31[7:0];
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assign mc[55:48] = s21[7:0];
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assign mc[47:40] = s11[7:0];
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assign mc[39:32] = s01[7:0];
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assign mc[31:24] = s30[7:0];
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assign mc[23:16] = s20[7:0];
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assign mc[15:8] = s10[7:0];
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assign mc[7:0] = s00[7:0];
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endmodule
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`define HERCULESAE_UNDEFINE
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`include "herculesae_header.sv"
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`undef HERCULESAE_UNDEFINE
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