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68 lines
1.4 KiB
68 lines
1.4 KiB
Xilinx Zynq Reset Manager |
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The Zynq AP-SoC has several different resets. |
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See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets. |
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Required properties: |
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- compatible: "xlnx,zynq-reset" |
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- reg: SLCR offset and size taken via syscon <0x200 0x48> |
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- syscon: <&slcr> |
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This should be a phandle to the Zynq's SLCR registers. |
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- #reset-cells: Must be 1 |
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The Zynq Reset Manager needs to be a childnode of the SLCR. |
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Example: |
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rstc: rstc@200 { |
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compatible = "xlnx,zynq-reset"; |
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reg = <0x200 0x48>; |
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#reset-cells = <1>; |
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syscon = <&slcr>; |
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}; |
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Reset outputs: |
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0 : soft reset |
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32 : ddr reset |
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64 : topsw reset |
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96 : dmac reset |
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128: usb0 reset |
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129: usb1 reset |
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160: gem0 reset |
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161: gem1 reset |
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164: gem0 rx reset |
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165: gem1 rx reset |
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166: gem0 ref reset |
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167: gem1 ref reset |
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192: sdio0 reset |
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193: sdio1 reset |
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196: sdio0 ref reset |
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197: sdio1 ref reset |
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224: spi0 reset |
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225: spi1 reset |
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226: spi0 ref reset |
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227: spi1 ref reset |
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256: can0 reset |
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257: can1 reset |
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258: can0 ref reset |
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259: can1 ref reset |
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288: i2c0 reset |
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289: i2c1 reset |
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320: uart0 reset |
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321: uart1 reset |
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322: uart0 ref reset |
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323: uart1 ref reset |
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352: gpio reset |
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384: lqspi reset |
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385: qspi ref reset |
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416: smc reset |
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417: smc ref reset |
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448: ocm reset |
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512: fpga0 out reset |
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513: fpga1 out reset |
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514: fpga2 out reset |
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515: fpga3 out reset |
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544: a9 reset 0 |
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545: a9 reset 1 |
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552: peri reset |
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