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55 lines
1.5 KiB
55 lines
1.5 KiB
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= Zynq UltraScale+ MPSoC and Versal reset driver binding = |
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The Zynq UltraScale+ MPSoC and Versal has several different resets. |
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See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information |
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about zynqmp resets. |
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Please also refer to reset.txt in this directory for common reset |
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controller binding usage. |
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Required Properties: |
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- compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform |
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"xlnx,versal-reset" for Versal platform |
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- #reset-cells: Specifies the number of cells needed to encode reset |
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line, should be 1 |
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------- |
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Example |
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------- |
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firmware { |
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zynqmp_firmware: zynqmp-firmware { |
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compatible = "xlnx,zynqmp-firmware"; |
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method = "smc"; |
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zynqmp_reset: reset-controller { |
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compatible = "xlnx,zynqmp-reset"; |
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#reset-cells = <1>; |
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}; |
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}; |
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}; |
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Specifying reset lines connected to IP modules |
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============================================== |
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Device nodes that need access to reset lines should |
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specify them as a reset phandle in their corresponding node as |
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specified in reset.txt. |
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For list of all valid reset indices for Zynq UltraScale+ MPSoC see |
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<dt-bindings/reset/xlnx-zynqmp-resets.h> |
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For list of all valid reset indices for Versal see |
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<dt-bindings/reset/xlnx-versal-resets.h> |
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Example: |
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serdes: zynqmp_phy@fd400000 { |
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... |
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resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; |
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reset-names = "sata_rst"; |
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... |
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};
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