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65 lines
1.4 KiB
65 lines
1.4 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Renesas RZ/G2L USBPHY Control |
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maintainers: |
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- Biju Das <[email protected]> |
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description: |
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The RZ/G2L USBPHY Control mainly controls reset and power down of the |
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USB/PHY. |
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properties: |
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compatible: |
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items: |
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- enum: |
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- renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} |
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- const: renesas,rzg2l-usbphy-ctrl |
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reg: |
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maxItems: 1 |
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clocks: |
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maxItems: 1 |
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resets: |
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maxItems: 1 |
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power-domains: |
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maxItems: 1 |
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'#reset-cells': |
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const: 1 |
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description: | |
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The phandle's argument in the reset specifier is the PHY reset associated |
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with the USB port. |
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0 = Port 1 Phy reset |
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1 = Port 2 Phy reset |
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required: |
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- compatible |
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- reg |
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- clocks |
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- resets |
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- power-domains |
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- '#reset-cells' |
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additionalProperties: false |
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examples: |
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- | |
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#include <dt-bindings/clock/r9a07g044-cpg.h> |
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phyrst: usbphy-ctrl@11c40000 { |
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compatible = "renesas,r9a07g044-usbphy-ctrl", |
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"renesas,rzg2l-usbphy-ctrl"; |
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reg = <0x11c40000 0x10000>; |
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clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>; |
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resets = <&cpg R9A07G044_USB_PRESETN>; |
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power-domains = <&cpg>; |
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#reset-cells = <1>; |
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};
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