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65 lines
1.6 KiB
65 lines
1.6 KiB
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: System Reset Controller on Intel Gateway SoCs |
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maintainers: |
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- Dilip Kota <[email protected]> |
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properties: |
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compatible: |
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enum: |
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- intel,rcu-lgm |
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- intel,rcu-xrx200 |
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reg: |
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description: Reset controller registers. |
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maxItems: 1 |
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intel,global-reset: |
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description: Global reset register offset and bit offset. |
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$ref: /schemas/types.yaml#/definitions/uint32-array |
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items: |
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- description: Register offset |
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- description: Register bit offset |
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minimum: 0 |
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maximum: 31 |
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"#reset-cells": |
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minimum: 2 |
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maximum: 3 |
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description: | |
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First cell is reset request register offset. |
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Second cell is bit offset in reset request register. |
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Third cell is bit offset in reset status register. |
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For LGM SoC, reset cell count is 2 as bit offset in |
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reset request and reset status registers is same. Whereas |
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3 for legacy SoCs as bit offset differs. |
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required: |
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- compatible |
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- reg |
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- intel,global-reset |
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- "#reset-cells" |
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additionalProperties: false |
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examples: |
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- | |
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rcu0: reset-controller@e0000000 { |
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compatible = "intel,rcu-lgm"; |
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reg = <0xe0000000 0x20000>; |
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intel,global-reset = <0x10 30>; |
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#reset-cells = <2>; |
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}; |
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pwm: pwm@e0d00000 { |
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compatible = "intel,lgm-pwm"; |
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reg = <0xe0d00000 0x30>; |
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clocks = <&cgu0 1>; |
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#pwm-cells = <2>; |
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resets = <&rcu0 0x30 21>; |
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};
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