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93 lines
2.3 KiB
93 lines
2.3 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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# Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/ |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Renesas R-Car PCIe Endpoint |
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maintainers: |
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- Lad Prabhakar <[email protected]> |
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- Yoshihiro Shimoda <[email protected]> |
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properties: |
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compatible: |
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items: |
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- enum: |
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- renesas,r8a774a1-pcie-ep # RZ/G2M |
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- renesas,r8a774b1-pcie-ep # RZ/G2N |
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- renesas,r8a774c0-pcie-ep # RZ/G2E |
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- renesas,r8a774e1-pcie-ep # RZ/G2H |
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- renesas,r8a7795-pcie-ep # R-Car H3 |
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- const: renesas,rcar-gen3-pcie-ep # R-Car Gen3 and RZ/G2 |
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reg: |
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maxItems: 5 |
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reg-names: |
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items: |
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- const: apb-base |
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- const: memory0 |
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- const: memory1 |
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- const: memory2 |
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- const: memory3 |
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interrupts: |
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minItems: 3 |
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maxItems: 3 |
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power-domains: |
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maxItems: 1 |
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resets: |
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maxItems: 1 |
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clocks: |
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maxItems: 1 |
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clock-names: |
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items: |
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- const: pcie |
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max-functions: |
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minimum: 1 |
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maximum: 1 |
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required: |
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- compatible |
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- reg |
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- reg-names |
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- interrupts |
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- resets |
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- power-domains |
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- clocks |
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- clock-names |
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- max-functions |
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additionalProperties: false |
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examples: |
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- | |
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#include <dt-bindings/clock/r8a774c0-cpg-mssr.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/power/r8a774c0-sysc.h> |
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pcie0_ep: pcie-ep@fe000000 { |
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compatible = "renesas,r8a774c0-pcie-ep", |
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"renesas,rcar-gen3-pcie-ep"; |
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reg = <0xfe000000 0x80000>, |
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<0xfe100000 0x100000>, |
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<0xfe200000 0x200000>, |
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<0x30000000 0x8000000>, |
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<0x38000000 0x8000000>; |
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reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; |
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; |
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resets = <&cpg 319>; |
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power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; |
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clocks = <&cpg CPG_MOD 319>; |
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clock-names = "pcie"; |
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max-functions = /bits/ 8 <1>; |
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};
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