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377 lines
11 KiB
377 lines
11 KiB
* Qualcomm PCI express root complex |
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- compatible: |
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Usage: required |
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Value type: <stringlist> |
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Definition: Value should contain |
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- "qcom,pcie-ipq8064" for ipq8064 |
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- "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065 |
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- "qcom,pcie-apq8064" for apq8064 |
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- "qcom,pcie-apq8084" for apq8084 |
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- "qcom,pcie-msm8996" for msm8996 or apq8096 |
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- "qcom,pcie-ipq4019" for ipq4019 |
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- "qcom,pcie-ipq8074" for ipq8074 |
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- "qcom,pcie-qcs404" for qcs404 |
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- "qcom,pcie-sc8180x" for sc8180x |
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- "qcom,pcie-sdm845" for sdm845 |
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- "qcom,pcie-sm8250" for sm8250 |
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- "qcom,pcie-ipq6018" for ipq6018 |
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- reg: |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: Register ranges as listed in the reg-names property |
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- reg-names: |
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Usage: required |
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Value type: <stringlist> |
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Definition: Must include the following entries |
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- "parf" Qualcomm specific registers |
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- "dbi" DesignWare PCIe registers |
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- "elbi" External local bus interface registers |
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- "config" PCIe configuration space |
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- "atu" ATU address space (optional) |
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- device_type: |
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Usage: required |
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Value type: <string> |
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Definition: Should be "pci". As specified in snps,dw-pcie.yaml |
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- #address-cells: |
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Usage: required |
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Value type: <u32> |
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Definition: Should be 3. As specified in snps,dw-pcie.yaml |
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- #size-cells: |
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Usage: required |
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Value type: <u32> |
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Definition: Should be 2. As specified in snps,dw-pcie.yaml |
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- ranges: |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: As specified in snps,dw-pcie.yaml |
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- interrupts: |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: MSI interrupt |
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- interrupt-names: |
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Usage: required |
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Value type: <stringlist> |
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Definition: Should contain "msi" |
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- #interrupt-cells: |
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Usage: required |
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Value type: <u32> |
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Definition: Should be 1. As specified in snps,dw-pcie.yaml |
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- interrupt-map-mask: |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: As specified in snps,dw-pcie.yaml |
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- interrupt-map: |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: As specified in snps,dw-pcie.yaml |
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- clocks: |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: List of phandle and clock specifier pairs as listed |
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in clock-names property |
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- clock-names: |
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Usage: required |
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Value type: <stringlist> |
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Definition: Should contain the following entries |
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- "iface" Configuration AHB clock |
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- clock-names: |
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Usage: required for ipq/apq8064 |
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Value type: <stringlist> |
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Definition: Should contain the following entries |
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- "core" Clocks the pcie hw block |
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- "phy" Clocks the pcie PHY block |
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- "aux" Clocks the pcie AUX block |
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- "ref" Clocks the pcie ref block |
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- clock-names: |
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Usage: required for apq8084/ipq4019 |
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Value type: <stringlist> |
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Definition: Should contain the following entries |
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- "aux" Auxiliary (AUX) clock |
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- "bus_master" Master AXI clock |
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- "bus_slave" Slave AXI clock |
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- clock-names: |
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Usage: required for msm8996/apq8096 |
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Value type: <stringlist> |
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Definition: Should contain the following entries |
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- "pipe" Pipe Clock driving internal logic |
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- "aux" Auxiliary (AUX) clock |
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- "cfg" Configuration clock |
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- "bus_master" Master AXI clock |
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- "bus_slave" Slave AXI clock |
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- clock-names: |
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Usage: required for ipq8074 |
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Value type: <stringlist> |
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Definition: Should contain the following entries |
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- "iface" PCIe to SysNOC BIU clock |
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- "axi_m" AXI Master clock |
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- "axi_s" AXI Slave clock |
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- "ahb" AHB clock |
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- "aux" Auxiliary clock |
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- clock-names: |
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Usage: required for ipq6018 |
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Value type: <stringlist> |
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Definition: Should contain the following entries |
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- "iface" PCIe to SysNOC BIU clock |
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- "axi_m" AXI Master clock |
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- "axi_s" AXI Slave clock |
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- "axi_bridge" AXI bridge clock |
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- "rchng" |
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- clock-names: |
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Usage: required for qcs404 |
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Value type: <stringlist> |
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Definition: Should contain the following entries |
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- "iface" AHB clock |
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- "aux" Auxiliary clock |
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- "master_bus" AXI Master clock |
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- "slave_bus" AXI Slave clock |
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- clock-names: |
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Usage: required for sdm845 |
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Value type: <stringlist> |
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Definition: Should contain the following entries |
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- "aux" Auxiliary clock |
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- "cfg" Configuration clock |
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- "bus_master" Master AXI clock |
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- "bus_slave" Slave AXI clock |
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- "slave_q2a" Slave Q2A clock |
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- "tbu" PCIe TBU clock |
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- "pipe" PIPE clock |
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- clock-names: |
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Usage: required for sc8180x and sm8250 |
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Value type: <stringlist> |
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Definition: Should contain the following entries |
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- "aux" Auxiliary clock |
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- "cfg" Configuration clock |
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- "bus_master" Master AXI clock |
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- "bus_slave" Slave AXI clock |
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- "slave_q2a" Slave Q2A clock |
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- "tbu" PCIe TBU clock |
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- "ddrss_sf_tbu" PCIe SF TBU clock |
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- "pipe" PIPE clock |
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- resets: |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: List of phandle and reset specifier pairs as listed |
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in reset-names property |
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- reset-names: |
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Usage: required for ipq/apq8064 |
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Value type: <stringlist> |
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Definition: Should contain the following entries |
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- "axi" AXI reset |
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- "ahb" AHB reset |
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- "por" POR reset |
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- "pci" PCI reset |
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- "phy" PHY reset |
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- reset-names: |
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Usage: required for apq8084 |
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Value type: <stringlist> |
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Definition: Should contain the following entries |
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- "core" Core reset |
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- reset-names: |
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Usage: required for ipq/apq8064 |
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Value type: <stringlist> |
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Definition: Should contain the following entries |
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- "axi_m" AXI master reset |
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- "axi_s" AXI slave reset |
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- "pipe" PIPE reset |
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- "axi_m_vmid" VMID reset |
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- "axi_s_xpu" XPU reset |
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- "parf" PARF reset |
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- "phy" PHY reset |
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- "axi_m_sticky" AXI sticky reset |
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- "pipe_sticky" PIPE sticky reset |
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- "pwr" PWR reset |
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- "ahb" AHB reset |
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- "phy_ahb" PHY AHB reset |
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- "ext" EXT reset |
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- reset-names: |
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Usage: required for ipq8074 |
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Value type: <stringlist> |
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Definition: Should contain the following entries |
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- "pipe" PIPE reset |
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- "sleep" Sleep reset |
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- "sticky" Core Sticky reset |
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- "axi_m" AXI Master reset |
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- "axi_s" AXI Slave reset |
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- "ahb" AHB Reset |
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- "axi_m_sticky" AXI Master Sticky reset |
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- reset-names: |
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Usage: required for ipq6018 |
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Value type: <stringlist> |
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Definition: Should contain the following entries |
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- "pipe" PIPE reset |
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- "sleep" Sleep reset |
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- "sticky" Core Sticky reset |
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- "axi_m" AXI Master reset |
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- "axi_s" AXI Slave reset |
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- "ahb" AHB Reset |
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- "axi_m_sticky" AXI Master Sticky reset |
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- "axi_s_sticky" AXI Slave Sticky reset |
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- reset-names: |
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Usage: required for qcs404 |
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Value type: <stringlist> |
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Definition: Should contain the following entries |
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- "axi_m" AXI Master reset |
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- "axi_s" AXI Slave reset |
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- "axi_m_sticky" AXI Master Sticky reset |
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- "pipe_sticky" PIPE sticky reset |
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- "pwr" PWR reset |
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- "ahb" AHB reset |
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- reset-names: |
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Usage: required for sc8180x, sdm845 and sm8250 |
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Value type: <stringlist> |
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Definition: Should contain the following entries |
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- "pci" PCIe core reset |
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- power-domains: |
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Usage: required for apq8084 and msm8996/apq8096 |
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Value type: <prop-encoded-array> |
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Definition: A phandle and power domain specifier pair to the |
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power domain which is responsible for collapsing |
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and restoring power to the peripheral |
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- vdda-supply: |
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Usage: required |
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Value type: <phandle> |
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Definition: A phandle to the core analog power supply |
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- vdda_phy-supply: |
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Usage: required for ipq/apq8064 |
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Value type: <phandle> |
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Definition: A phandle to the analog power supply for PHY |
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- vdda_refclk-supply: |
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Usage: required for ipq/apq8064 |
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Value type: <phandle> |
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Definition: A phandle to the analog power supply for IC which generates |
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reference clock |
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- vddpe-3v3-supply: |
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Usage: optional |
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Value type: <phandle> |
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Definition: A phandle to the PCIe endpoint power supply |
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- phys: |
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Usage: required for apq8084 and qcs404 |
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Value type: <phandle> |
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Definition: List of phandle(s) as listed in phy-names property |
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- phy-names: |
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Usage: required for apq8084 and qcs404 |
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Value type: <stringlist> |
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Definition: Should contain "pciephy" |
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- <name>-gpios: |
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Usage: optional |
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Value type: <prop-encoded-array> |
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Definition: List of phandle and GPIO specifier pairs. Should contain |
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- "perst-gpios" PCIe endpoint reset signal line |
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- "wake-gpios" PCIe endpoint wake signal line |
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* Example for ipq/apq8064 |
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pcie@1b500000 { |
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compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie"; |
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reg = <0x1b500000 0x1000 |
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0x1b502000 0x80 |
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0x1b600000 0x100 |
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0x0ff00000 0x100000>; |
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reg-names = "dbi", "elbi", "parf", "config"; |
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device_type = "pci"; |
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linux,pci-domain = <0>; |
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bus-range = <0x00 0xff>; |
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num-lanes = <1>; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ |
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0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */ |
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interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>; |
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interrupt-names = "msi"; |
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#interrupt-cells = <1>; |
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interrupt-map-mask = <0 0 0 0x7>; |
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interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ |
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<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ |
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<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ |
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<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ |
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clocks = <&gcc PCIE_A_CLK>, |
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<&gcc PCIE_H_CLK>, |
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<&gcc PCIE_PHY_CLK>, |
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<&gcc PCIE_AUX_CLK>, |
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<&gcc PCIE_ALT_REF_CLK>; |
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clock-names = "core", "iface", "phy", "aux", "ref"; |
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resets = <&gcc PCIE_ACLK_RESET>, |
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<&gcc PCIE_HCLK_RESET>, |
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<&gcc PCIE_POR_RESET>, |
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<&gcc PCIE_PCI_RESET>, |
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<&gcc PCIE_PHY_RESET>, |
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<&gcc PCIE_EXT_RESET>; |
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reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; |
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pinctrl-0 = <&pcie_pins_default>; |
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pinctrl-names = "default"; |
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}; |
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* Example for apq8084 |
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pcie0@fc520000 { |
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compatible = "qcom,pcie-apq8084", "snps,dw-pcie"; |
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reg = <0xfc520000 0x2000>, |
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<0xff000000 0x1000>, |
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<0xff001000 0x1000>, |
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<0xff002000 0x2000>; |
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reg-names = "parf", "dbi", "elbi", "config"; |
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device_type = "pci"; |
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linux,pci-domain = <0>; |
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bus-range = <0x00 0xff>; |
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num-lanes = <1>; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */ |
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0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */ |
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interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>; |
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interrupt-names = "msi"; |
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#interrupt-cells = <1>; |
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interrupt-map-mask = <0 0 0 0x7>; |
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interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ |
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<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ |
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<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ |
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<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ |
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clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, |
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>, |
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>, |
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<&gcc GCC_PCIE_0_AUX_CLK>; |
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clock-names = "iface", "master_bus", "slave_bus", "aux"; |
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resets = <&gcc GCC_PCIE_0_BCR>; |
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reset-names = "core"; |
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power-domains = <&gcc PCIE0_GDSC>; |
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vdda-supply = <&pma8084_l3>; |
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phys = <&pciephy0>; |
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phy-names = "pciephy"; |
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perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>; |
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pinctrl-0 = <&pcie0_pins_default>; |
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pinctrl-names = "default"; |
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};
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