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72 lines
2.4 KiB
72 lines
2.4 KiB
* Mobiveil AXI PCIe Root Port Bridge DT description |
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Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP |
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has up to 8 outbound and inbound windows for the address translation. |
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Required properties: |
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- #address-cells: Address representation for root ports, set to <3> |
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- #size-cells: Size representation for root ports, set to <2> |
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- #interrupt-cells: specifies the number of cells needed to encode an |
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interrupt source. The value must be 1. |
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- compatible: Should contain "mbvl,gpex40-pcie" |
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- reg: Should contain PCIe registers location and length |
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Mandatory: |
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"config_axi_slave": PCIe controller registers |
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"csr_axi_slave" : Bridge config registers |
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Optional: |
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"gpio_slave" : GPIO registers to control slot power |
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"apb_csr" : MSI registers |
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- device_type: must be "pci" |
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- apio-wins : number of requested apio outbound windows |
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default 2 outbound windows are configured - |
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1. Config window |
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2. Memory window |
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- ppio-wins : number of requested ppio inbound windows |
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default 1 inbound memory window is configured. |
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- bus-range: PCI bus numbers covered |
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- interrupt-controller: identifies the node as an interrupt controller |
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- #interrupt-cells: specifies the number of cells needed to encode an |
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interrupt source. The value must be 1. |
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- interrupts: The interrupt line of the PCIe controller |
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last cell of this field is set to 4 to |
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denote it as IRQ_TYPE_LEVEL_HIGH type interrupt. |
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- interrupt-map-mask, |
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interrupt-map: standard PCI properties to define the mapping of the |
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PCI interface to interrupt numbers. |
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- ranges: ranges for the PCI memory regions (I/O space region is not |
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supported by hardware) |
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Please refer to the standard PCI bus binding document for a more |
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detailed explanation |
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Example: |
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++++++++ |
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pcie0: pcie@a0000000 { |
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#address-cells = <3>; |
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#size-cells = <2>; |
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compatible = "mbvl,gpex40-pcie"; |
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reg = <0xa0000000 0x00001000>, |
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<0xb0000000 0x00010000>, |
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<0xff000000 0x00200000>, |
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<0xb0010000 0x00001000>; |
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reg-names = "config_axi_slave", |
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"csr_axi_slave", |
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"gpio_slave", |
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"apb_csr"; |
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device_type = "pci"; |
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apio-wins = <2>; |
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ppio-wins = <1>; |
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bus-range = <0x00000000 0x000000ff>; |
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interrupt-controller; |
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interrupt-parent = <&gic>; |
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#interrupt-cells = <1>; |
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interrupts = < 0 89 4 >; |
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interrupt-map-mask = <0 0 0 7>; |
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interrupt-map = <0 0 0 0 &pci_express 0>, |
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<0 0 0 1 &pci_express 1>, |
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<0 0 0 2 &pci_express 2>, |
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<0 0 0 3 &pci_express 3>; |
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ranges = < 0x83000000 0 0x00000000 0xa8000000 0 0x8000000>; |
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};
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