forked from Qortal/Brooklyn
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
145 lines
3.8 KiB
145 lines
3.8 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
|
%YAML 1.2 |
|
--- |
|
$id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml# |
|
$schema: http://devicetree.org/meta-schemas/core.yaml# |
|
|
|
title: MediaTek MT7621 PCIe controller |
|
|
|
maintainers: |
|
- Sergio Paracuellos <[email protected]> |
|
|
|
description: |+ |
|
MediaTek MT7621 PCIe subsys supports a single Root Complex (RC) |
|
with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link |
|
|
|
allOf: |
|
- $ref: /schemas/pci/pci-bus.yaml# |
|
|
|
properties: |
|
compatible: |
|
const: mediatek,mt7621-pci |
|
|
|
reg: |
|
items: |
|
- description: host-pci bridge registers |
|
- description: pcie port 0 RC control registers |
|
- description: pcie port 1 RC control registers |
|
- description: pcie port 2 RC control registers |
|
|
|
ranges: |
|
maxItems: 2 |
|
|
|
patternProperties: |
|
'pcie@[0-2],0': |
|
type: object |
|
$ref: /schemas/pci/pci-bus.yaml# |
|
|
|
properties: |
|
resets: |
|
maxItems: 1 |
|
|
|
clocks: |
|
maxItems: 1 |
|
|
|
phys: |
|
maxItems: 1 |
|
|
|
phy-names: |
|
pattern: '^pcie-phy[0-2]$' |
|
|
|
required: |
|
- "#interrupt-cells" |
|
- interrupt-map-mask |
|
- interrupt-map |
|
- resets |
|
- clocks |
|
- phys |
|
- phy-names |
|
- ranges |
|
|
|
unevaluatedProperties: false |
|
|
|
required: |
|
- compatible |
|
- reg |
|
- ranges |
|
- "#interrupt-cells" |
|
- interrupt-map-mask |
|
- interrupt-map |
|
- reset-gpios |
|
|
|
unevaluatedProperties: false |
|
|
|
examples: |
|
- | |
|
#include <dt-bindings/gpio/gpio.h> |
|
#include <dt-bindings/interrupt-controller/mips-gic.h> |
|
|
|
pcie: pcie@1e140000 { |
|
compatible = "mediatek,mt7621-pci"; |
|
reg = <0x1e140000 0x100>, |
|
<0x1e142000 0x100>, |
|
<0x1e143000 0x100>, |
|
<0x1e144000 0x100>; |
|
|
|
#address-cells = <3>; |
|
#size-cells = <2>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&pcie_pins>; |
|
device_type = "pci"; |
|
ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */ |
|
<0x01000000 0 0x1e160000 0x1e160000 0 0x00010000>; /* io space */ |
|
#interrupt-cells = <1>; |
|
interrupt-map-mask = <0xF800 0 0 0>; |
|
interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, |
|
<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, |
|
<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; |
|
reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; |
|
|
|
pcie@0,0 { |
|
reg = <0x0000 0 0 0 0>; |
|
#address-cells = <3>; |
|
#size-cells = <2>; |
|
device_type = "pci"; |
|
#interrupt-cells = <1>; |
|
interrupt-map-mask = <0 0 0 0>; |
|
interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; |
|
resets = <&rstctrl 24>; |
|
clocks = <&clkctrl 24>; |
|
phys = <&pcie0_phy 1>; |
|
phy-names = "pcie-phy0"; |
|
ranges; |
|
}; |
|
|
|
pcie@1,0 { |
|
reg = <0x0800 0 0 0 0>; |
|
#address-cells = <3>; |
|
#size-cells = <2>; |
|
device_type = "pci"; |
|
#interrupt-cells = <1>; |
|
interrupt-map-mask = <0 0 0 0>; |
|
interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; |
|
resets = <&rstctrl 25>; |
|
clocks = <&clkctrl 25>; |
|
phys = <&pcie0_phy 1>; |
|
phy-names = "pcie-phy1"; |
|
ranges; |
|
}; |
|
|
|
pcie@2,0 { |
|
reg = <0x1000 0 0 0 0>; |
|
#address-cells = <3>; |
|
#size-cells = <2>; |
|
device_type = "pci"; |
|
#interrupt-cells = <1>; |
|
interrupt-map-mask = <0 0 0 0>; |
|
interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; |
|
resets = <&rstctrl 26>; |
|
clocks = <&clkctrl 26>; |
|
phys = <&pcie2_phy 0>; |
|
phy-names = "pcie-phy2"; |
|
ranges; |
|
}; |
|
}; |
|
...
|
|
|