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50 lines
1.8 KiB
50 lines
1.8 KiB
HiSilicon Kirin SoCs PCIe host DT description |
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Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. |
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It shares common functions with the PCIe DesignWare core driver and |
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inherits common properties defined in |
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Documentation/devicetree/bindings/pci/designware-pcie.txt. |
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Additional properties are described here: |
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Required properties |
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- compatible: |
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"hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC |
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- reg: Should contain rc_dbi, apb, phy, config registers location and length. |
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- reg-names: Must include the following entries: |
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"dbi": controller configuration registers; |
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"apb": apb Ctrl register defined by Kirin; |
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"phy": apb PHY register defined by Kirin; |
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"config": PCIe configuration space registers. |
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- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. |
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Optional properties: |
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Example based on kirin960: |
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pcie@f4000000 { |
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compatible = "hisilicon,kirin-pcie"; |
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reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, |
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<0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; |
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reg-names = "dbi","apb","phy", "config"; |
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bus-range = <0x0 0x1>; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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device_type = "pci"; |
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ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; |
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num-lanes = <1>; |
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#interrupt-cells = <1>; |
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interrupt-map-mask = <0xf800 0 0 7>; |
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interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, |
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<0x0 0 0 2 &gic 0 0 0 283 4>, |
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<0x0 0 0 3 &gic 0 0 0 284 4>, |
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<0x0 0 0 4 &gic 0 0 0 285 4>; |
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clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, |
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<&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, |
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<&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, |
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<&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, |
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<&crg_ctrl HI3660_ACLK_GATE_PCIE>; |
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clock-names = "pcie_phy_ref", "pcie_aux", |
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"pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; |
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reset-gpios = <&gpio11 1 0 >; |
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};
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