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97 lines
2.2 KiB
97 lines
2.2 KiB
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: "http://devicetree.org/schemas/pci/intel,keembay-pcie.yaml#" |
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$schema: "http://devicetree.org/meta-schemas/core.yaml#" |
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title: Intel Keem Bay PCIe controller Root Complex mode |
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maintainers: |
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- Wan Ahmad Zainie <[email protected]> |
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- Srikanth Thokala <[email protected]> |
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allOf: |
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- $ref: /schemas/pci/pci-bus.yaml# |
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properties: |
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compatible: |
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const: intel,keembay-pcie |
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ranges: |
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maxItems: 1 |
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reset-gpios: |
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maxItems: 1 |
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reg: |
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maxItems: 4 |
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reg-names: |
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items: |
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- const: dbi |
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- const: atu |
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- const: config |
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- const: apb |
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clocks: |
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maxItems: 2 |
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clock-names: |
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items: |
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- const: master |
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- const: aux |
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interrupts: |
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maxItems: 3 |
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interrupt-names: |
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items: |
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- const: pcie |
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- const: pcie_ev |
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- const: pcie_err |
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num-lanes: |
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description: Number of lanes to use. |
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enum: [ 1, 2 ] |
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required: |
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- compatible |
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- reg |
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- reg-names |
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- ranges |
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- clocks |
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- clock-names |
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- interrupts |
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- interrupt-names |
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- reset-gpios |
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unevaluatedProperties: false |
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examples: |
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- | |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/interrupt-controller/irq.h> |
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#include <dt-bindings/gpio/gpio.h> |
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#define KEEM_BAY_A53_PCIE |
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#define KEEM_BAY_A53_AUX_PCIE |
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pcie@37000000 { |
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compatible = "intel,keembay-pcie"; |
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reg = <0x37000000 0x00001000>, |
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<0x37300000 0x00001000>, |
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<0x36e00000 0x00200000>, |
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<0x37800000 0x00000200>; |
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reg-names = "dbi", "atu", "config", "apb"; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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device_type = "pci"; |
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ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>; |
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "pcie", "pcie_ev", "pcie_err"; |
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clocks = <&scmi_clk KEEM_BAY_A53_PCIE>, |
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<&scmi_clk KEEM_BAY_A53_AUX_PCIE>; |
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clock-names = "master", "aux"; |
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reset-gpios = <&pca2 9 GPIO_ACTIVE_LOW>; |
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num-lanes = <2>; |
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};
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