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174 lines
4.3 KiB
174 lines
4.3 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/pci/apple,pcie.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Apple PCIe host controller |
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maintainers: |
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- Mark Kettenis <[email protected]> |
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description: | |
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The Apple PCIe host controller is a PCIe host controller with |
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multiple root ports present in Apple ARM SoC platforms, including |
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various iPhone and iPad devices and the "Apple Silicon" Macs. |
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The controller incorporates Synopsys DesigWare PCIe logic to |
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implements its root ports. But the ATU found on most DesignWare |
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PCIe host bridges is absent. |
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All root ports share a single ECAM space, but separate GPIOs are |
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used to take the PCI devices on those ports out of reset. Therefore |
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the standard "reset-gpios" and "max-link-speed" properties appear on |
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the child nodes that represent the PCI bridges that correspond to |
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the individual root ports. |
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MSIs are handled by the PCIe controller and translated into regular |
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interrupts. A range of 32 MSIs is provided. These 32 MSIs can be |
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distributed over the root ports as the OS sees fit by programming |
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the PCIe controller's port registers. |
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properties: |
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compatible: |
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items: |
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- enum: |
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- apple,t8103-pcie |
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- apple,t6000-pcie |
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- const: apple,pcie |
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reg: |
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minItems: 3 |
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maxItems: 6 |
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reg-names: |
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minItems: 3 |
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items: |
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- const: config |
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- const: rc |
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- const: port0 |
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- const: port1 |
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- const: port2 |
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- const: port3 |
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ranges: |
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minItems: 2 |
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maxItems: 2 |
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interrupts: |
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description: |
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Interrupt specifiers, one for each root port. |
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minItems: 1 |
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maxItems: 4 |
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msi-parent: true |
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msi-ranges: |
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maxItems: 1 |
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iommu-map: true |
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iommu-map-mask: true |
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required: |
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- compatible |
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- reg |
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- reg-names |
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- bus-range |
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- interrupts |
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- msi-controller |
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- msi-parent |
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- msi-ranges |
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unevaluatedProperties: false |
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allOf: |
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- $ref: /schemas/pci/pci-bus.yaml# |
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- $ref: /schemas/interrupt-controller/msi-controller.yaml# |
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- if: |
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properties: |
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compatible: |
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contains: |
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const: apple,t8103-pcie |
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then: |
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properties: |
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reg: |
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maxItems: 5 |
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interrupts: |
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maxItems: 3 |
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examples: |
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- | |
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#include <dt-bindings/interrupt-controller/apple-aic.h> |
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soc { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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pcie0: pcie@690000000 { |
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compatible = "apple,t8103-pcie", "apple,pcie"; |
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device_type = "pci"; |
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reg = <0x6 0x90000000 0x0 0x1000000>, |
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<0x6 0x80000000 0x0 0x100000>, |
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<0x6 0x81000000 0x0 0x4000>, |
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<0x6 0x82000000 0x0 0x4000>, |
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<0x6 0x83000000 0x0 0x4000>; |
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reg-names = "config", "rc", "port0", "port1", "port2"; |
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interrupt-parent = <&aic>; |
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interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, |
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<AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, |
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<AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; |
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msi-controller; |
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msi-parent = <&pcie0>; |
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msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; |
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iommu-map = <0x100 &dart0 1 1>, |
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<0x200 &dart1 1 1>, |
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<0x300 &dart2 1 1>; |
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iommu-map-mask = <0xff00>; |
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bus-range = <0 3>; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, |
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<0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; |
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power-domains = <&ps_apcie>, <&ps_apcie_gp>, <&ps_pcie_ref>; |
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pinctrl-0 = <&pcie_pins>; |
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pinctrl-names = "default"; |
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pci@0,0 { |
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device_type = "pci"; |
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reg = <0x0 0x0 0x0 0x0 0x0>; |
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reset-gpios = <&pinctrl_ap 152 0>; |
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max-link-speed = <2>; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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ranges; |
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}; |
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pci@1,0 { |
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device_type = "pci"; |
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reg = <0x800 0x0 0x0 0x0 0x0>; |
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reset-gpios = <&pinctrl_ap 153 0>; |
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max-link-speed = <2>; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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ranges; |
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}; |
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pci@2,0 { |
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device_type = "pci"; |
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reg = <0x1000 0x0 0x0 0x0 0x0>; |
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reset-gpios = <&pinctrl_ap 33 0>; |
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max-link-speed = <1>; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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ranges; |
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}; |
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}; |
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};
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