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59 lines
1.9 KiB
59 lines
1.9 KiB
Aardvark PCIe controller |
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This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC. |
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The Device Tree node describing an Aardvark PCIe controller must |
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contain the following properties: |
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- compatible: Should be "marvell,armada-3700-pcie" |
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- reg: range of registers for the PCIe controller |
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- interrupts: the interrupt line of the PCIe controller |
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- #address-cells: set to <3> |
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- #size-cells: set to <2> |
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- device_type: set to "pci" |
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- ranges: ranges for the PCI memory and I/O regions |
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- #interrupt-cells: set to <1> |
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- msi-controller: indicates that the PCIe controller can itself |
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handle MSI interrupts |
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- msi-parent: pointer to the MSI controller to be used |
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- interrupt-map-mask and interrupt-map: standard PCI properties to |
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define the mapping of the PCIe interface to interrupt numbers. |
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- bus-range: PCI bus numbers covered |
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- phys: the PCIe PHY handle |
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- max-link-speed: see pci.txt |
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- reset-gpios: see pci.txt |
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In addition, the Device Tree describing an Aardvark PCIe controller |
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must include a sub-node that describes the legacy interrupt controller |
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built into the PCIe controller. This sub-node must have the following |
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properties: |
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- interrupt-controller |
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- #interrupt-cells: set to <1> |
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Example: |
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pcie0: pcie@d0070000 { |
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compatible = "marvell,armada-3700-pcie"; |
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device_type = "pci"; |
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reg = <0 0xd0070000 0 0x20000>; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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bus-range = <0x00 0xff>; |
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
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#interrupt-cells = <1>; |
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msi-controller; |
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msi-parent = <&pcie0>; |
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ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ |
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0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ |
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interrupt-map-mask = <0 0 0 7>; |
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interrupt-map = <0 0 0 1 &pcie_intc 0>, |
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<0 0 0 2 &pcie_intc 1>, |
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<0 0 0 3 &pcie_intc 2>, |
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<0 0 0 4 &pcie_intc 3>; |
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phys = <&comphy1 0>; |
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pcie_intc: interrupt-controller { |
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interrupt-controller; |
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#interrupt-cells = <1>; |
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}; |
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};
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