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129 lines
3.1 KiB
129 lines
3.1 KiB
Common MDIO bus multiplexer/switch properties. |
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An MDIO bus multiplexer/switch will have several child busses that are |
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numbered uniquely in a device dependent manner. The nodes for an MDIO |
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bus multiplexer/switch will have one child node for each child bus. |
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Required properties: |
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- #address-cells = <1>; |
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- #size-cells = <0>; |
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Optional properties: |
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- mdio-parent-bus : phandle to the parent MDIO bus. |
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- Other properties specific to the multiplexer/switch hardware. |
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Required properties for child nodes: |
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- #address-cells = <1>; |
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- #size-cells = <0>; |
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- reg : The sub-bus number. |
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Example : |
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/* The parent MDIO bus. */ |
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smi1: mdio@1180000001900 { |
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compatible = "cavium,octeon-3860-mdio"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x11800 0x00001900 0x0 0x40>; |
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}; |
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/* |
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An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a |
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pair of GPIO lines. Child busses 2 and 3 populated with 4 |
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PHYs each. |
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*/ |
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mdio-mux { |
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compatible = "mdio-mux-gpio"; |
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gpios = <&gpio1 3 0>, <&gpio1 4 0>; |
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mdio-parent-bus = <&smi1>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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mdio@2 { |
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reg = <2>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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phy11: ethernet-phy@1 { |
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reg = <1>; |
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marvell,reg-init = <3 0x10 0 0x5777>, |
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<3 0x11 0 0x00aa>, |
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<3 0x12 0 0x4105>, |
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<3 0x13 0 0x0a60>; |
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interrupt-parent = <&gpio>; |
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interrupts = <10 8>; /* Pin 10, active low */ |
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}; |
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phy12: ethernet-phy@2 { |
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reg = <2>; |
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marvell,reg-init = <3 0x10 0 0x5777>, |
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<3 0x11 0 0x00aa>, |
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<3 0x12 0 0x4105>, |
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<3 0x13 0 0x0a60>; |
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interrupt-parent = <&gpio>; |
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interrupts = <10 8>; /* Pin 10, active low */ |
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}; |
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phy13: ethernet-phy@3 { |
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reg = <3>; |
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marvell,reg-init = <3 0x10 0 0x5777>, |
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<3 0x11 0 0x00aa>, |
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<3 0x12 0 0x4105>, |
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<3 0x13 0 0x0a60>; |
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interrupt-parent = <&gpio>; |
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interrupts = <10 8>; /* Pin 10, active low */ |
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}; |
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phy14: ethernet-phy@4 { |
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reg = <4>; |
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marvell,reg-init = <3 0x10 0 0x5777>, |
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<3 0x11 0 0x00aa>, |
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<3 0x12 0 0x4105>, |
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<3 0x13 0 0x0a60>; |
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interrupt-parent = <&gpio>; |
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interrupts = <10 8>; /* Pin 10, active low */ |
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}; |
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}; |
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mdio@3 { |
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reg = <3>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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phy21: ethernet-phy@1 { |
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reg = <1>; |
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marvell,reg-init = <3 0x10 0 0x5777>, |
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<3 0x11 0 0x00aa>, |
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<3 0x12 0 0x4105>, |
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<3 0x13 0 0x0a60>; |
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interrupt-parent = <&gpio>; |
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interrupts = <12 8>; /* Pin 12, active low */ |
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}; |
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phy22: ethernet-phy@2 { |
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reg = <2>; |
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marvell,reg-init = <3 0x10 0 0x5777>, |
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<3 0x11 0 0x00aa>, |
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<3 0x12 0 0x4105>, |
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<3 0x13 0 0x0a60>; |
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interrupt-parent = <&gpio>; |
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interrupts = <12 8>; /* Pin 12, active low */ |
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}; |
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phy23: ethernet-phy@3 { |
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reg = <3>; |
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marvell,reg-init = <3 0x10 0 0x5777>, |
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<3 0x11 0 0x00aa>, |
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<3 0x12 0 0x4105>, |
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<3 0x13 0 0x0a60>; |
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interrupt-parent = <&gpio>; |
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interrupts = <12 8>; /* Pin 12, active low */ |
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}; |
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phy24: ethernet-phy@4 { |
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reg = <4>; |
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marvell,reg-init = <3 0x10 0 0x5777>, |
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<3 0x11 0 0x00aa>, |
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<3 0x12 0 0x4105>, |
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<3 0x13 0 0x0a60>; |
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interrupt-parent = <&gpio>; |
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interrupts = <12 8>; /* Pin 12, active low */ |
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}; |
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}; |
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};
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