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205 lines
7.8 KiB
205 lines
7.8 KiB
4xx/Axon EMAC ethernet nodes |
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The EMAC ethernet controller in IBM and AMCC 4xx chips, and also |
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the Axon bridge. To operate this needs to interact with a this |
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special McMAL DMA controller, and sometimes an RGMII or ZMII |
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interface. In addition to the nodes and properties described |
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below, the node for the OPB bus on which the EMAC sits must have a |
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correct clock-frequency property. |
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i) The EMAC node itself |
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Required properties: |
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- device_type : "network" |
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- compatible : compatible list, contains 2 entries, first is |
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"ibm,emac-CHIP" where CHIP is the host ASIC (440gx, |
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405gp, Axon) and second is either "ibm,emac" or |
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"ibm,emac4". For Axon, thus, we have: "ibm,emac-axon", |
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"ibm,emac4" |
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- interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ> |
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- reg : <registers mapping> |
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- local-mac-address : 6 bytes, MAC address |
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- mal-device : phandle of the associated McMAL node |
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- mal-tx-channel : 1 cell, index of the tx channel on McMAL associated |
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with this EMAC |
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- mal-rx-channel : 1 cell, index of the rx channel on McMAL associated |
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with this EMAC |
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- cell-index : 1 cell, hardware index of the EMAC cell on a given |
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ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on |
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each Axon chip) |
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- max-frame-size : 1 cell, maximum frame size supported in bytes |
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- rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec |
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operations. |
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For Axon, 2048 |
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- tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec |
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operations. |
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For Axon, 2048. |
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- fifo-entry-size : 1 cell, size of a fifo entry (used to calculate |
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thresholds). |
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For Axon, 0x00000010 |
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- mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds) |
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in bytes. |
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For Axon, 0x00000100 (I think ...) |
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- phy-mode : string, mode of operations of the PHY interface. |
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Supported values are: "mii", "rmii", "smii", "rgmii", |
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"tbi", "gmii", rtbi", "sgmii". |
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For Axon on CAB, it is "rgmii" |
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- mdio-device : 1 cell, required iff using shared MDIO registers |
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(440EP). phandle of the EMAC to use to drive the |
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MDIO lines for the PHY used by this EMAC. |
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- zmii-device : 1 cell, required iff connected to a ZMII. phandle of |
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the ZMII device node |
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- zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII |
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channel or 0xffffffff if ZMII is only used for MDIO. |
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- rgmii-device : 1 cell, required iff connected to an RGMII. phandle |
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of the RGMII device node. |
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For Axon: phandle of plb5/plb4/opb/rgmii |
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- rgmii-channel : 1 cell, required iff connected to an RGMII. Which |
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RGMII channel is used by this EMAC. |
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Fox Axon: present, whatever value is appropriate for each |
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EMAC, that is the content of the current (bogus) "phy-port" |
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property. |
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Optional properties: |
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- phy-address : 1 cell, optional, MDIO address of the PHY. If absent, |
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a search is performed. |
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- phy-map : 1 cell, optional, bitmap of addresses to probe the PHY |
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for, used if phy-address is absent. bit 0x00000001 is |
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MDIO address 0. |
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For Axon it can be absent, though my current driver |
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doesn't handle phy-address yet so for now, keep |
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0x00ffffff in it. |
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- phy-handle : Used to describe configurations where a external PHY |
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is used. Please refer to: |
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Documentation/devicetree/bindings/net/ethernet.txt |
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- rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec |
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operations (if absent the value is the same as |
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rx-fifo-size). For Axon, either absent or 2048. |
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- tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec |
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operations (if absent the value is the same as |
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tx-fifo-size). For Axon, either absent or 2048. |
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- tah-device : 1 cell, optional. If connected to a TAH engine for |
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offload, phandle of the TAH device node. |
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- tah-channel : 1 cell, optional. If appropriate, channel used on the |
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TAH engine. |
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- fixed-link : Fixed-link subnode describing a link to a non-MDIO |
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managed entity. See |
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Documentation/devicetree/bindings/net/fixed-link.txt |
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for details. |
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- mdio subnode : When the EMAC has a phy connected to its local |
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mdio, which us supported by the kernel's network |
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PHY library in drivers/net/phy, there must be device |
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tree subnode with the following required properties: |
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- #address-cells: Must be <1>. |
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- #size-cells: Must be <0>. |
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For PHY definitions: Please refer to |
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Documentation/devicetree/bindings/net/phy.txt and |
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Documentation/devicetree/bindings/net/ethernet.txt |
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Examples: |
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EMAC0: ethernet@40000800 { |
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device_type = "network"; |
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compatible = "ibm,emac-440gp", "ibm,emac"; |
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interrupt-parent = <&UIC1>; |
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interrupts = <1c 4 1d 4>; |
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reg = <40000800 70>; |
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local-mac-address = [00 04 AC E3 1B 1E]; |
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mal-device = <&MAL0>; |
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mal-tx-channel = <0 1>; |
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mal-rx-channel = <0>; |
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cell-index = <0>; |
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max-frame-size = <5dc>; |
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rx-fifo-size = <1000>; |
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tx-fifo-size = <800>; |
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phy-mode = "rmii"; |
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phy-map = <00000001>; |
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zmii-device = <&ZMII0>; |
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zmii-channel = <0>; |
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}; |
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EMAC1: ethernet@ef600c00 { |
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device_type = "network"; |
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compatible = "ibm,emac-apm821xx", "ibm,emac4sync"; |
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interrupt-parent = <&EMAC1>; |
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interrupts = <0 1>; |
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#interrupt-cells = <1>; |
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#address-cells = <0>; |
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#size-cells = <0>; |
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interrupt-map = <0 &UIC2 0x10 IRQ_TYPE_LEVEL_HIGH /* Status */ |
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1 &UIC2 0x14 IRQ_TYPE_LEVEL_HIGH /* Wake */>; |
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reg = <0xef600c00 0x000000c4>; |
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local-mac-address = [000000000000]; /* Filled in by U-Boot */ |
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mal-device = <&MAL0>; |
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mal-tx-channel = <0>; |
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mal-rx-channel = <0>; |
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cell-index = <0>; |
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max-frame-size = <9000>; |
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rx-fifo-size = <16384>; |
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tx-fifo-size = <2048>; |
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fifo-entry-size = <10>; |
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phy-mode = "rgmii"; |
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phy-handle = <&phy0>; |
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phy-map = <0x00000000>; |
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rgmii-device = <&RGMII0>; |
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rgmii-channel = <0>; |
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tah-device = <&TAH0>; |
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tah-channel = <0>; |
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has-inverted-stacr-oc; |
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has-new-stacr-staopc; |
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mdio { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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phy0: ethernet-phy@0 { |
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compatible = "ethernet-phy-ieee802.3-c22"; |
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reg = <0>; |
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}; |
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}; |
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}; |
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ii) McMAL node |
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Required properties: |
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- device_type : "dma-controller" |
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- compatible : compatible list, containing 2 entries, first is |
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"ibm,mcmal-CHIP" where CHIP is the host ASIC (like |
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emac) and the second is either "ibm,mcmal" or |
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"ibm,mcmal2". |
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For Axon, "ibm,mcmal-axon","ibm,mcmal2" |
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- interrupts : <interrupt mapping for the MAL interrupts sources: |
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5 sources: tx_eob, rx_eob, serr, txde, rxde>. |
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For Axon: This is _different_ from the current |
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firmware. We use the "delayed" interrupts for txeob |
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and rxeob. Thus we end up with mapping those 5 MPIC |
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interrupts, all level positive sensitive: 10, 11, 32, |
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33, 34 (in decimal) |
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- dcr-reg : < DCR registers range > |
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- dcr-parent : if needed for dcr-reg |
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- num-tx-chans : 1 cell, number of Tx channels |
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- num-rx-chans : 1 cell, number of Rx channels |
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iii) ZMII node |
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Required properties: |
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- compatible : compatible list, containing 2 entries, first is |
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"ibm,zmii-CHIP" where CHIP is the host ASIC (like |
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EMAC) and the second is "ibm,zmii". |
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For Axon, there is no ZMII node. |
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- reg : <registers mapping> |
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iv) RGMII node |
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Required properties: |
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- compatible : compatible list, containing 2 entries, first is |
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"ibm,rgmii-CHIP" where CHIP is the host ASIC (like |
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EMAC) and the second is "ibm,rgmii". |
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For Axon, "ibm,rgmii-axon","ibm,rgmii" |
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- reg : <registers mapping> |
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- revision : as provided by the RGMII new version register if |
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available. |
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For Axon: 0x0000012a
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