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663 lines
16 KiB
663 lines
16 KiB
============================================================================= |
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Freescale Frame Manager Device Bindings |
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|
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CONTENTS |
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- FMan Node |
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- FMan Port Node |
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- FMan MURAM Node |
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- FMan dTSEC/XGEC/mEMAC Node |
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- FMan IEEE 1588 Node |
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- FMan MDIO Node |
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- Example |
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|
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============================================================================= |
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FMan Node |
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DESCRIPTION |
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|
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Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs, |
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etc.) the FMan node will have child nodes for each of them. |
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|
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PROPERTIES |
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|
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- compatible |
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Usage: required |
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Value type: <stringlist> |
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Definition: Must include "fsl,fman" |
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FMan version can be determined via FM_IP_REV_1 register in the |
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FMan block. The offset is 0xc4 from the beginning of the |
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Frame Processing Manager memory map (0xc3000 from the |
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beginning of the FMan node). |
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|
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- cell-index |
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Usage: required |
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Value type: <u32> |
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Definition: Specifies the index of the FMan unit. |
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|
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The cell-index value may be used by the SoC, to identify the |
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FMan unit in the SoC memory map. In the table below, |
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there's a description of the cell-index use in each SoC: |
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|
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- P1023: |
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register[bit] FMan unit cell-index |
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============================================================ |
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DEVDISR[1] 1 0 |
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|
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- P2041, P3041, P4080 P5020, P5040: |
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register[bit] FMan unit cell-index |
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============================================================ |
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DCFG_DEVDISR2[6] 1 0 |
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DCFG_DEVDISR2[14] 2 1 |
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(Second FM available only in P4080 and P5040) |
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|
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- B4860, T1040, T2080, T4240: |
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register[bit] FMan unit cell-index |
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============================================================ |
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DCFG_CCSR_DEVDISR2[24] 1 0 |
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DCFG_CCSR_DEVDISR2[25] 2 1 |
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(Second FM available only in T4240) |
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|
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DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in |
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the specific SoC "Device Configuration/Pin Control" Memory |
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Map. |
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- reg |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: A standard property. Specifies the offset of the |
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following configuration registers: |
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- BMI configuration registers. |
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- QMI configuration registers. |
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- DMA configuration registers. |
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- FPM configuration registers. |
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- FMan controller configuration registers. |
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|
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- ranges |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: A standard property. |
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|
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- clocks |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: phandle for the fman input clock. |
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|
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- clock-names |
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usage: required |
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Value type: <stringlist> |
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Definition: "fmanclk" for the fman input clock. |
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|
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- interrupts |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: A pair of IRQs are specified in this property. |
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The first element is associated with the event interrupts and |
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the second element is associated with the error interrupts. |
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|
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- fsl,qman-channel-range |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: Specifies the range of the available dedicated |
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channels in the FMan. The first cell specifies the beginning |
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of the range and the second cell specifies the number of |
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channels. |
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Further information available at: |
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"Work Queue (WQ) Channel Assignments in the QMan" section |
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in DPAA Reference Manual. |
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|
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- fsl,qman |
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- fsl,bman |
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Usage: required |
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Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt |
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|
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- fsl,erratum-a050385 |
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Usage: optional |
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Value type: boolean |
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Definition: A boolean property. Indicates the presence of the |
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erratum A050385 which indicates that DMA transactions that are |
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split can result in a FMan lock. |
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|
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============================================================================= |
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FMan MURAM Node |
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|
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DESCRIPTION |
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|
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FMan Internal memory - shared between all the FMan modules. |
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It contains data structures that are common and written to or read by |
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the modules. |
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FMan internal memory is split into the following parts: |
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Packet buffering (Tx/Rx FIFOs) |
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Frames internal context |
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|
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PROPERTIES |
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- compatible |
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Usage: required |
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Value type: <stringlist> |
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Definition: Must include "fsl,fman-muram" |
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|
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- ranges |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: A standard property. |
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Specifies the multi-user memory offset and the size within |
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the FMan. |
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|
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EXAMPLE |
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muram@0 { |
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compatible = "fsl,fman-muram"; |
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ranges = <0 0x000000 0x28000>; |
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}; |
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============================================================================= |
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FMan Port Node |
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|
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DESCRIPTION |
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|
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The Frame Manager (FMan) supports several types of hardware ports: |
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Ethernet receiver (RX) |
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Ethernet transmitter (TX) |
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Offline/Host command (O/H) |
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|
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PROPERTIES |
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- compatible |
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Usage: required |
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Value type: <stringlist> |
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Definition: A standard property. |
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Must include one of the following: |
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- "fsl,fman-v2-port-oh" for FManV2 OH ports |
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- "fsl,fman-v2-port-rx" for FManV2 RX ports |
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- "fsl,fman-v2-port-tx" for FManV2 TX ports |
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- "fsl,fman-v3-port-oh" for FManV3 OH ports |
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- "fsl,fman-v3-port-rx" for FManV3 RX ports |
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- "fsl,fman-v3-port-tx" for FManV3 TX ports |
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|
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- cell-index |
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Usage: required |
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Value type: <u32> |
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Definition: Specifies the hardware port id. |
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Each hardware port on the FMan has its own hardware PortID. |
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Super set of all hardware Port IDs available at FMan Reference |
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Manual under "FMan Hardware Ports in Freescale Devices" table. |
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|
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Each hardware port is assigned a 4KB, port-specific page in |
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the FMan hardware port memory region (which is part of the |
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FMan memory map). The first 4 KB in the FMan hardware ports |
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memory region is used for what are called common registers. |
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The subsequent 63 4KB pages are allocated to the hardware |
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ports. |
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The page of a specific port is determined by the cell-index. |
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- reg |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: There is one reg region describing the port |
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configuration registers. |
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|
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- fsl,fman-10g-port |
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Usage: optional |
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Value type: boolean |
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Definition: The default port rate is 1G. |
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If this property exists, the port is s 10G port. |
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|
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- fsl,fman-best-effort-port |
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Usage: optional |
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Value type: boolean |
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Definition: Can be defined only if 10G-support is set. |
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This property marks a best-effort 10G port (10G port that |
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may not be capable of line rate). |
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EXAMPLE |
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port@a8000 { |
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cell-index = <0x28>; |
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compatible = "fsl,fman-v2-port-tx"; |
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reg = <0xa8000 0x1000>; |
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}; |
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port@88000 { |
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cell-index = <0x8>; |
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compatible = "fsl,fman-v2-port-rx"; |
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reg = <0x88000 0x1000>; |
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}; |
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port@81000 { |
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cell-index = <0x1>; |
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compatible = "fsl,fman-v2-port-oh"; |
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reg = <0x81000 0x1000>; |
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}; |
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|
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============================================================================= |
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FMan dTSEC/XGEC/mEMAC Node |
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|
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DESCRIPTION |
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mEMAC/dTSEC/XGEC are the Ethernet network interfaces |
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PROPERTIES |
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- compatible |
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Usage: required |
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Value type: <stringlist> |
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Definition: A standard property. |
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Must include one of the following: |
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- "fsl,fman-dtsec" for dTSEC MAC |
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- "fsl,fman-xgec" for XGEC MAC |
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- "fsl,fman-memac" for mEMAC MAC |
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|
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- cell-index |
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Usage: required |
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Value type: <u32> |
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Definition: Specifies the MAC id. |
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|
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The cell-index value may be used by the FMan or the SoC, to |
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identify the MAC unit in the FMan (or SoC) memory map. |
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In the tables below there's a description of the cell-index |
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use, there are two tables, one describes the use of cell-index |
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by the FMan, the second describes the use by the SoC: |
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|
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1. FMan Registers |
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FManV2: |
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register[bit] MAC cell-index |
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============================================================ |
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FM_EPI[16] XGEC 8 |
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FM_EPI[16+n] dTSECn n-1 |
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FM_NPI[11+n] dTSECn n-1 |
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n = 1,..,5 |
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FManV3: |
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register[bit] MAC cell-index |
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============================================================ |
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FM_EPI[16+n] mEMACn n-1 |
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FM_EPI[25] mEMAC10 9 |
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FM_NPI[11+n] mEMACn n-1 |
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FM_NPI[10] mEMAC10 9 |
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FM_NPI[11] mEMAC9 8 |
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n = 1,..8 |
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|
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FM_EPI and FM_NPI are located in the FMan memory map. |
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|
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2. SoC registers: |
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|
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- P2041, P3041, P4080 P5020, P5040: |
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register[bit] FMan MAC cell |
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Unit index |
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============================================================ |
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DCFG_DEVDISR2[7] 1 XGEC 8 |
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DCFG_DEVDISR2[7+n] 1 dTSECn n-1 |
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DCFG_DEVDISR2[15] 2 XGEC 8 |
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DCFG_DEVDISR2[15+n] 2 dTSECn n-1 |
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n = 1,..5 |
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|
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- T1040, T2080, T4240, B4860: |
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register[bit] FMan MAC cell |
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Unit index |
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============================================================ |
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DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1 |
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DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1 |
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n = 1,..6,9,10 |
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|
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EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in |
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the specific SoC "Device Configuration/Pin Control" Memory |
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Map. |
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- reg |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: A standard property. |
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|
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- fsl,fman-ports |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: An array of two phandles - the first references is |
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the FMan RX port and the second is the TX port used by this |
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MAC. |
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|
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- ptp-timer |
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Usage required |
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Value type: <phandle> |
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Definition: A phandle for 1EEE1588 timer. |
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|
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- pcsphy-handle |
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Usage required for "fsl,fman-memac" MACs |
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Value type: <phandle> |
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Definition: A phandle for pcsphy. |
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|
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- tbi-handle |
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Usage required for "fsl,fman-dtsec" MACs |
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Value type: <phandle> |
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Definition: A phandle for tbiphy. |
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|
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EXAMPLE |
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fman1_tx28: port@a8000 { |
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cell-index = <0x28>; |
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compatible = "fsl,fman-v2-port-tx"; |
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reg = <0xa8000 0x1000>; |
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}; |
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fman1_rx8: port@88000 { |
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cell-index = <0x8>; |
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compatible = "fsl,fman-v2-port-rx"; |
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reg = <0x88000 0x1000>; |
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}; |
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ptp-timer: ptp_timer@fe000 { |
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compatible = "fsl,fman-ptp-timer"; |
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reg = <0xfe000 0x1000>; |
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}; |
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ethernet@e0000 { |
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compatible = "fsl,fman-dtsec"; |
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cell-index = <0>; |
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reg = <0xe0000 0x1000>; |
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fsl,fman-ports = <&fman1_rx8 &fman1_tx28>; |
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ptp-timer = <&ptp-timer>; |
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tbi-handle = <&tbi0>; |
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}; |
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|
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============================================================================ |
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FMan IEEE 1588 Node |
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|
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Refer to Documentation/devicetree/bindings/ptp/ptp-qoriq.txt |
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|
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============================================================================= |
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FMan MDIO Node |
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|
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DESCRIPTION |
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|
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The MDIO is a bus to which the PHY devices are connected. |
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PROPERTIES |
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- compatible |
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Usage: required |
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Value type: <stringlist> |
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Definition: A standard property. |
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Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2. |
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Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2. |
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Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from |
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FMan v3. |
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|
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- reg |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: A standard property. |
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|
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- bus-frequency |
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Usage: optional |
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Value type: <u32> |
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Definition: Specifies the external MDIO bus clock speed to |
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be used, if different from the standard 2.5 MHz. |
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This may be due to the standard speed being unsupported (e.g. |
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due to a hardware problem), or to advertise that all relevant |
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components in the system support a faster speed. |
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|
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- interrupts |
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Usage: required for external MDIO |
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Value type: <prop-encoded-array> |
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Definition: Event interrupt of external MDIO controller. |
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|
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- fsl,fman-internal-mdio |
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Usage: required for internal MDIO |
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Value type: boolean |
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Definition: Fman has internal MDIO for internal PCS(Physical |
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Coding Sublayer) PHYs and external MDIO for external PHYs. |
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The settings and programming routines for internal/external |
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MDIO are different. Must be included for internal MDIO. |
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|
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- fsl,erratum-a009885 |
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Usage: optional |
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Value type: <boolean> |
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Definition: Indicates the presence of the A009885 |
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erratum describing that the contents of MDIO_DATA may |
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become corrupt unless it is read within 16 MDC cycles |
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of MDIO_CFG[BSY] being cleared, when performing an |
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MDIO read operation. |
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|
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- fsl,erratum-a011043 |
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Usage: optional |
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Value type: <boolean> |
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Definition: Indicates the presence of the A011043 erratum |
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describing that the MDIO_CFG[MDIO_RD_ER] bit may be falsely |
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set when reading internal PCS registers. MDIO reads to |
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internal PCS registers may result in having the |
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MDIO_CFG[MDIO_RD_ER] bit set, even when there is no error and |
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read data (MDIO_DATA[MDIO_DATA]) is correct. |
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Software may get false read error when reading internal |
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PCS registers through MDIO. As a workaround, all internal |
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MDIO accesses should ignore the MDIO_CFG[MDIO_RD_ER] bit. |
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|
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For internal PHY device on internal mdio bus, a PHY node should be created. |
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See the definition of the PHY node in booting-without-of.txt for an |
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example of how to define a PHY (Internal PHY has no interrupt line). |
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- For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY. |
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- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY, |
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PCS PHY addr must be '0'. |
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|
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EXAMPLE |
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Example for FMan v2 external MDIO: |
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mdio@f1000 { |
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compatible = "fsl,fman-xmdio"; |
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reg = <0xf1000 0x1000>; |
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interrupts = <101 2 0 0>; |
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}; |
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|
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Example for FMan v2 internal MDIO: |
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mdio@e3120 { |
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compatible = "fsl,fman-mdio"; |
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reg = <0xe3120 0xee0>; |
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fsl,fman-internal-mdio; |
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|
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tbi1: tbi-phy@8 { |
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reg = <0x8>; |
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device_type = "tbi-phy"; |
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}; |
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}; |
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Example for FMan v3 internal MDIO: |
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mdio@f1000 { |
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compatible = "fsl,fman-memac-mdio"; |
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reg = <0xf1000 0x1000>; |
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fsl,fman-internal-mdio; |
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|
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pcsphy6: ethernet-phy@0 { |
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reg = <0x0>; |
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}; |
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}; |
|
|
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============================================================================= |
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Example |
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fman@400000 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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cell-index = <1>; |
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compatible = "fsl,fman" |
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ranges = <0 0x400000 0x100000>; |
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reg = <0x400000 0x100000>; |
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clocks = <&fman_clk>; |
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clock-names = "fmanclk"; |
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interrupts = < |
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96 2 0 0 |
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16 2 1 1>; |
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fsl,qman-channel-range = <0x40 0xc>; |
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|
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muram@0 { |
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compatible = "fsl,fman-muram"; |
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reg = <0x0 0x28000>; |
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}; |
|
|
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port@81000 { |
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cell-index = <1>; |
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compatible = "fsl,fman-v2-port-oh"; |
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reg = <0x81000 0x1000>; |
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}; |
|
|
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port@82000 { |
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cell-index = <2>; |
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compatible = "fsl,fman-v2-port-oh"; |
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reg = <0x82000 0x1000>; |
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}; |
|
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port@83000 { |
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cell-index = <3>; |
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compatible = "fsl,fman-v2-port-oh"; |
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reg = <0x83000 0x1000>; |
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}; |
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port@84000 { |
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cell-index = <4>; |
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compatible = "fsl,fman-v2-port-oh"; |
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reg = <0x84000 0x1000>; |
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}; |
|
|
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port@85000 { |
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cell-index = <5>; |
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compatible = "fsl,fman-v2-port-oh"; |
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reg = <0x85000 0x1000>; |
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}; |
|
|
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port@86000 { |
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cell-index = <6>; |
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compatible = "fsl,fman-v2-port-oh"; |
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reg = <0x86000 0x1000>; |
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}; |
|
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fman1_rx_0x8: port@88000 { |
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cell-index = <0x8>; |
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compatible = "fsl,fman-v2-port-rx"; |
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reg = <0x88000 0x1000>; |
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}; |
|
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fman1_rx_0x9: port@89000 { |
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cell-index = <0x9>; |
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compatible = "fsl,fman-v2-port-rx"; |
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reg = <0x89000 0x1000>; |
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}; |
|
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fman1_rx_0xa: port@8a000 { |
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cell-index = <0xa>; |
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compatible = "fsl,fman-v2-port-rx"; |
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reg = <0x8a000 0x1000>; |
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}; |
|
|
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fman1_rx_0xb: port@8b000 { |
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cell-index = <0xb>; |
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compatible = "fsl,fman-v2-port-rx"; |
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reg = <0x8b000 0x1000>; |
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}; |
|
|
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fman1_rx_0xc: port@8c000 { |
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cell-index = <0xc>; |
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compatible = "fsl,fman-v2-port-rx"; |
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reg = <0x8c000 0x1000>; |
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}; |
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fman1_rx_0x10: port@90000 { |
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cell-index = <0x10>; |
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compatible = "fsl,fman-v2-port-rx"; |
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reg = <0x90000 0x1000>; |
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}; |
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|
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fman1_tx_0x28: port@a8000 { |
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cell-index = <0x28>; |
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compatible = "fsl,fman-v2-port-tx"; |
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reg = <0xa8000 0x1000>; |
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}; |
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|
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fman1_tx_0x29: port@a9000 { |
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cell-index = <0x29>; |
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compatible = "fsl,fman-v2-port-tx"; |
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reg = <0xa9000 0x1000>; |
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}; |
|
|
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fman1_tx_0x2a: port@aa000 { |
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cell-index = <0x2a>; |
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compatible = "fsl,fman-v2-port-tx"; |
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reg = <0xaa000 0x1000>; |
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}; |
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fman1_tx_0x2b: port@ab000 { |
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cell-index = <0x2b>; |
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compatible = "fsl,fman-v2-port-tx"; |
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reg = <0xab000 0x1000>; |
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}; |
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|
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fman1_tx_0x2c: port@ac0000 { |
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cell-index = <0x2c>; |
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compatible = "fsl,fman-v2-port-tx"; |
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reg = <0xac000 0x1000>; |
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}; |
|
|
|
fman1_tx_0x30: port@b0000 { |
|
cell-index = <0x30>; |
|
compatible = "fsl,fman-v2-port-tx"; |
|
reg = <0xb0000 0x1000>; |
|
}; |
|
|
|
ethernet@e0000 { |
|
compatible = "fsl,fman-dtsec"; |
|
cell-index = <0>; |
|
reg = <0xe0000 0x1000>; |
|
fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>; |
|
tbi-handle = <&tbi5>; |
|
}; |
|
|
|
ethernet@e2000 { |
|
compatible = "fsl,fman-dtsec"; |
|
cell-index = <1>; |
|
reg = <0xe2000 0x1000>; |
|
fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>; |
|
tbi-handle = <&tbi6>; |
|
}; |
|
|
|
ethernet@e4000 { |
|
compatible = "fsl,fman-dtsec"; |
|
cell-index = <2>; |
|
reg = <0xe4000 0x1000>; |
|
fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>; |
|
tbi-handle = <&tbi7>; |
|
}; |
|
|
|
ethernet@e6000 { |
|
compatible = "fsl,fman-dtsec"; |
|
cell-index = <3>; |
|
reg = <0xe6000 0x1000>; |
|
fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>; |
|
tbi-handle = <&tbi8>; |
|
}; |
|
|
|
ethernet@e8000 { |
|
compatible = "fsl,fman-dtsec"; |
|
cell-index = <4>; |
|
reg = <0xf0000 0x1000>; |
|
fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>; |
|
tbi-handle = <&tbi9>; |
|
|
|
ethernet@f0000 { |
|
cell-index = <8>; |
|
compatible = "fsl,fman-xgec"; |
|
reg = <0xf0000 0x1000>; |
|
fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>; |
|
}; |
|
|
|
ptp-timer@fe000 { |
|
compatible = "fsl,fman-ptp-timer"; |
|
reg = <0xfe000 0x1000>; |
|
}; |
|
|
|
mdio@f1000 { |
|
compatible = "fsl,fman-xmdio"; |
|
reg = <0xf1000 0x1000>; |
|
interrupts = <101 2 0 0>; |
|
}; |
|
};
|
|
|