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240 lines
5.1 KiB
240 lines
5.1 KiB
Realtek SMI-based Switches |
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========================== |
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The SMI "Simple Management Interface" is a two-wire protocol using |
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bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does |
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not use the MDIO protocol. This binding defines how to specify the |
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SMI-based Realtek devices. |
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Required properties: |
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- compatible: must be exactly one of: |
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"realtek,rtl8365mb" (4+1 ports) |
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"realtek,rtl8366" |
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"realtek,rtl8366rb" (4+1 ports) |
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"realtek,rtl8366s" (4+1 ports) |
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"realtek,rtl8367" |
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"realtek,rtl8367b" |
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"realtek,rtl8368s" (8 port) |
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"realtek,rtl8369" |
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"realtek,rtl8370" (8 port) |
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Required properties: |
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- mdc-gpios: GPIO line for the MDC clock line. |
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- mdio-gpios: GPIO line for the MDIO data line. |
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- reset-gpios: GPIO line for the reset signal. |
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Optional properties: |
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- realtek,disable-leds: if the LED drivers are not used in the |
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hardware design this will disable them so they are not turned on |
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and wasting power. |
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Required subnodes: |
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- interrupt-controller |
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This defines an interrupt controller with an IRQ line (typically |
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a GPIO) that will demultiplex and handle the interrupt from the single |
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interrupt line coming out of one of the SMI-based chips. It most |
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importantly provides link up/down interrupts to the PHY blocks inside |
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the ASIC. |
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Required properties of interrupt-controller: |
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- interrupt: parent interrupt, see interrupt-controller/interrupts.txt |
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- interrupt-controller: see interrupt-controller/interrupts.txt |
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- #address-cells: should be <0> |
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- #interrupt-cells: should be <1> |
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- mdio |
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This defines the internal MDIO bus of the SMI device, mostly for the |
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purpose of being able to hook the interrupts to the right PHY and |
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the right PHY to the corresponding port. |
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Required properties of mdio: |
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- compatible: should be set to "realtek,smi-mdio" for all SMI devices |
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See net/mdio.txt for additional MDIO bus properties. |
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See net/dsa/dsa.txt for a list of additional required and optional properties |
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and subnodes of DSA switches. |
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Examples: |
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An example for the RTL8366RB: |
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switch { |
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compatible = "realtek,rtl8366rb"; |
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/* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ |
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mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; |
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mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; |
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reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; |
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switch_intc: interrupt-controller { |
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/* GPIO 15 provides the interrupt */ |
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interrupt-parent = <&gpio0>; |
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interrupts = <15 IRQ_TYPE_LEVEL_LOW>; |
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interrupt-controller; |
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#address-cells = <0>; |
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#interrupt-cells = <1>; |
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}; |
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0>; |
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port@0 { |
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reg = <0>; |
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label = "lan0"; |
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phy-handle = <&phy0>; |
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}; |
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port@1 { |
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reg = <1>; |
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label = "lan1"; |
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phy-handle = <&phy1>; |
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}; |
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port@2 { |
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reg = <2>; |
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label = "lan2"; |
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phy-handle = <&phy2>; |
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}; |
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port@3 { |
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reg = <3>; |
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label = "lan3"; |
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phy-handle = <&phy3>; |
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}; |
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port@4 { |
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reg = <4>; |
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label = "wan"; |
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phy-handle = <&phy4>; |
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}; |
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port@5 { |
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reg = <5>; |
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label = "cpu"; |
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ethernet = <&gmac0>; |
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phy-mode = "rgmii"; |
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fixed-link { |
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speed = <1000>; |
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full-duplex; |
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}; |
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}; |
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}; |
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mdio { |
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compatible = "realtek,smi-mdio", "dsa-mdio"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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phy0: phy@0 { |
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reg = <0>; |
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interrupt-parent = <&switch_intc>; |
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interrupts = <0>; |
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}; |
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phy1: phy@1 { |
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reg = <1>; |
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interrupt-parent = <&switch_intc>; |
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interrupts = <1>; |
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}; |
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phy2: phy@2 { |
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reg = <2>; |
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interrupt-parent = <&switch_intc>; |
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interrupts = <2>; |
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}; |
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phy3: phy@3 { |
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reg = <3>; |
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interrupt-parent = <&switch_intc>; |
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interrupts = <3>; |
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}; |
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phy4: phy@4 { |
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reg = <4>; |
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interrupt-parent = <&switch_intc>; |
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interrupts = <12>; |
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}; |
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}; |
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}; |
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An example for the RTL8365MB-VC: |
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switch { |
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compatible = "realtek,rtl8365mb"; |
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mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; |
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mdio-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; |
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reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; |
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switch_intc: interrupt-controller { |
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interrupt-parent = <&gpio5>; |
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interrupts = <1 IRQ_TYPE_LEVEL_LOW>; |
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interrupt-controller; |
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#address-cells = <0>; |
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#interrupt-cells = <1>; |
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}; |
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0>; |
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port@0 { |
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reg = <0>; |
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label = "swp0"; |
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phy-handle = <ðphy0>; |
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}; |
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port@1 { |
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reg = <1>; |
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label = "swp1"; |
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phy-handle = <ðphy1>; |
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}; |
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port@2 { |
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reg = <2>; |
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label = "swp2"; |
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phy-handle = <ðphy2>; |
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}; |
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port@3 { |
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reg = <3>; |
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label = "swp3"; |
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phy-handle = <ðphy3>; |
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}; |
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port@6 { |
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reg = <6>; |
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label = "cpu"; |
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ethernet = <&fec1>; |
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phy-mode = "rgmii"; |
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tx-internal-delay-ps = <2000>; |
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rx-internal-delay-ps = <2000>; |
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fixed-link { |
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speed = <1000>; |
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full-duplex; |
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pause; |
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}; |
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}; |
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}; |
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mdio { |
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compatible = "realtek,smi-mdio"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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ethphy0: phy@0 { |
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reg = <0>; |
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interrupt-parent = <&switch_intc>; |
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interrupts = <0>; |
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}; |
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ethphy1: phy@1 { |
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reg = <1>; |
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interrupt-parent = <&switch_intc>; |
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interrupts = <1>; |
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}; |
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ethphy2: phy@2 { |
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reg = <2>; |
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interrupt-parent = <&switch_intc>; |
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interrupts = <2>; |
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}; |
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ethphy3: phy@3 { |
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reg = <3>; |
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interrupt-parent = <&switch_intc>; |
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interrupts = <3>; |
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}; |
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}; |
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};
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