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148 lines
2.9 KiB
148 lines
2.9 KiB
Atheros AR9331 built-in switch |
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It is a switch built-in to Atheros AR9331 WiSoC and addressable over internal |
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MDIO bus. All PHYs are built-in as well. |
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Required properties: |
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- compatible: should be: "qca,ar9331-switch" |
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- reg: Address on the MII bus for the switch. |
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- resets : Must contain an entry for each entry in reset-names. |
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- reset-names : Must include the following entries: "switch" |
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- interrupt-parent: Phandle to the parent interrupt controller |
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- interrupts: IRQ line for the switch |
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- interrupt-controller: Indicates the switch is itself an interrupt |
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controller. This is used for the PHY interrupts. |
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- #interrupt-cells: must be 1 |
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- mdio: Container of PHY and devices on the switches MDIO bus. |
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See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional |
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required and optional properties. |
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Examples: |
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eth0: ethernet@19000000 { |
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compatible = "qca,ar9330-eth"; |
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reg = <0x19000000 0x200>; |
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interrupts = <4>; |
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resets = <&rst 9>, <&rst 22>; |
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reset-names = "mac", "mdio"; |
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clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; |
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clock-names = "eth", "mdio"; |
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phy-mode = "mii"; |
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phy-handle = <&phy_port4>; |
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}; |
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eth1: ethernet@1a000000 { |
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compatible = "qca,ar9330-eth"; |
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reg = <0x1a000000 0x200>; |
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interrupts = <5>; |
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resets = <&rst 13>, <&rst 23>; |
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reset-names = "mac", "mdio"; |
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clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; |
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clock-names = "eth", "mdio"; |
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phy-mode = "gmii"; |
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fixed-link { |
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speed = <1000>; |
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full-duplex; |
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}; |
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mdio { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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switch10: switch@10 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "qca,ar9331-switch"; |
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reg = <0x10>; |
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resets = <&rst 8>; |
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reset-names = "switch"; |
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interrupt-parent = <&miscintc>; |
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interrupts = <12>; |
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interrupt-controller; |
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#interrupt-cells = <1>; |
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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switch_port0: port@0 { |
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reg = <0x0>; |
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label = "cpu"; |
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ethernet = <ð1>; |
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phy-mode = "gmii"; |
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fixed-link { |
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speed = <1000>; |
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full-duplex; |
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}; |
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}; |
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switch_port1: port@1 { |
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reg = <0x1>; |
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phy-handle = <&phy_port0>; |
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phy-mode = "internal"; |
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}; |
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switch_port2: port@2 { |
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reg = <0x2>; |
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phy-handle = <&phy_port1>; |
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phy-mode = "internal"; |
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}; |
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switch_port3: port@3 { |
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reg = <0x3>; |
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phy-handle = <&phy_port2>; |
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phy-mode = "internal"; |
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}; |
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switch_port4: port@4 { |
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reg = <0x4>; |
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phy-handle = <&phy_port3>; |
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phy-mode = "internal"; |
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}; |
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}; |
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mdio { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupt-parent = <&switch10>; |
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phy_port0: phy@0 { |
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reg = <0x0>; |
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interrupts = <0>; |
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}; |
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phy_port1: phy@1 { |
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reg = <0x1>; |
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interrupts = <0>; |
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}; |
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phy_port2: phy@2 { |
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reg = <0x2>; |
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interrupts = <0>; |
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}; |
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phy_port3: phy@3 { |
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reg = <0x3>; |
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interrupts = <0>; |
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}; |
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phy_port4: phy@4 { |
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reg = <0x4>; |
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interrupts = <0>; |
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}; |
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}; |
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}; |
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}; |
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};
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