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110 lines
2.7 KiB
110 lines
2.7 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210) |
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maintainers: |
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- Thierry Reding <[email protected]> |
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- Jon Hunter <[email protected]> |
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properties: |
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compatible: |
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oneOf: |
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- enum: |
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- nvidia,tegra20-gpio |
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- nvidia,tegra30-gpio |
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- items: |
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- enum: |
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- nvidia,tegra114-gpio |
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- nvidia,tegra124-gpio |
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- nvidia,tegra210-gpio |
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- const: nvidia,tegra30-gpio |
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reg: |
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maxItems: 1 |
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interrupts: |
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description: The interrupt outputs from the controller. For Tegra20, |
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there should be 7 interrupts specified, and for Tegra30, there should |
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be 8 interrupts specified. |
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"#gpio-cells": |
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description: The first cell is the pin number and the second cell is used |
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to specify the GPIO polarity (0 = active high, 1 = active low). |
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const: 2 |
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gpio-controller: true |
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gpio-ranges: |
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maxItems: 1 |
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"#interrupt-cells": |
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description: | |
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Should be 2. The first cell is the GPIO number. The second cell is |
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used to specify flags: |
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bits[3:0] trigger type and level flags: |
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1 = low-to-high edge triggered. |
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2 = high-to-low edge triggered. |
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4 = active high level-sensitive. |
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8 = active low level-sensitive. |
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Valid combinations are 1, 2, 3, 4, 8. |
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const: 2 |
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interrupt-controller: true |
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allOf: |
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- if: |
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properties: |
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compatible: |
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contains: |
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const: nvidia,tegra30-gpio |
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then: |
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properties: |
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interrupts: |
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minItems: 8 |
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maxItems: 8 |
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else: |
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properties: |
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interrupts: |
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minItems: 7 |
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maxItems: 7 |
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required: |
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- compatible |
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- reg |
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- interrupts |
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- "#gpio-cells" |
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- gpio-controller |
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- "#interrupt-cells" |
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- interrupt-controller |
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additionalProperties: |
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type: object |
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required: |
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- gpio-hog |
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examples: |
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- | |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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gpio: gpio@6000d000 { |
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compatible = "nvidia,tegra20-gpio"; |
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reg = <0x6000d000 0x1000>; |
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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#interrupt-cells = <2>; |
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interrupt-controller; |
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};
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