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99 lines
2.5 KiB
99 lines
2.5 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/gpio/gpio-stp-xway.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Lantiq SoC Serial To Parallel (STP) GPIO controller |
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description: | |
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The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a |
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peripheral controller used to drive external shift register cascades. At most |
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3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem |
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and Ethernet PHYs to drive some bytes of the cascade automatically. |
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maintainers: |
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- John Crispin <[email protected]> |
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properties: |
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$nodename: |
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pattern: "^gpio@[0-9a-f]+$" |
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compatible: |
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const: lantiq,gpio-stp-xway |
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reg: |
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maxItems: 1 |
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gpio-controller: true |
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"#gpio-cells": |
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description: |
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The first cell is the pin number and the second cell is used to specify |
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consumer flags. |
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const: 2 |
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lantiq,shadow: |
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description: |
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The default value that we shall assume as already set on the |
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shift register cascade. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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minimum: 0x000000 |
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maximum: 0xffffff |
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lantiq,groups: |
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description: |
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Set the 3 bit mask to select which of the 3 groups are enabled |
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in the shift register cascade. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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minimum: 0x0 |
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maximum: 0x7 |
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lantiq,dsl: |
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description: |
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The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit |
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property can enable this feature. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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minimum: 0x0 |
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maximum: 0x3 |
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lantiq,rising: |
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description: |
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Use rising instead of falling edge for the shift register. |
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type: boolean |
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patternProperties: |
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"^lantiq,phy[1-4]$": |
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description: |
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The gphy core can control 3 bits of the gpio cascade. In the xRX200 family |
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phy[1-2] are available, in xRX330 phy[1-3] and in XRX330 phy[1-4]. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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minimum: 0x0 |
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maximum: 0x7 |
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required: |
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- compatible |
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- reg |
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- gpio-controller |
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- "#gpio-cells" |
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additionalProperties: false |
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examples: |
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- | |
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gpio@e100bb0 { |
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compatible = "lantiq,gpio-stp-xway"; |
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reg = <0xE100BB0 0x40>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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pinctrl-0 = <&stp_pins>; |
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pinctrl-names = "default"; |
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lantiq,shadow = <0xffffff>; |
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lantiq,groups = <0x7>; |
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lantiq,dsl = <0x3>; |
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lantiq,phy1 = <0x7>; |
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lantiq,phy2 = <0x7>; |
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}; |
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...
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