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42 lines
1.5 KiB
42 lines
1.5 KiB
Lantiq SoC Serial To Parallel (STP) GPIO controller |
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The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a |
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peripheral controller used to drive external shift register cascades. At most |
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3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem |
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to drive the 2 LSBs of the cascade automatically. |
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Required properties: |
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- compatible : Should be "lantiq,gpio-stp-xway" |
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- reg : Address and length of the register set for the device |
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- #gpio-cells : Should be two. The first cell is the pin number and |
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the second cell is used to specify optional parameters (currently |
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unused). |
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- gpio-controller : Marks the device node as a gpio controller. |
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Optional properties: |
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- lantiq,shadow : The default value that we shall assume as already set on the |
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shift register cascade. |
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- lantiq,groups : Set the 3 bit mask to select which of the 3 groups are enabled |
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in the shift register cascade. |
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- lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit |
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property can enable this feature. |
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- lantiq,phy1 : The gphy1 core can control 3 bits of the gpio cascade. |
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- lantiq,phy2 : The gphy2 core can control 3 bits of the gpio cascade. |
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- lantiq,rising : use rising instead of falling edge for the shift register |
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Example: |
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gpio1: stp@e100bb0 { |
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compatible = "lantiq,gpio-stp-xway"; |
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reg = <0xE100BB0 0x40>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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lantiq,shadow = <0xffff>; |
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lantiq,groups = <0x7>; |
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lantiq,dsl = <0x3>; |
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lantiq,phy1 = <0x7>; |
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lantiq,phy2 = <0x7>; |
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/* lantiq,rising; */ |
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};
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