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238 lines
7.3 KiB
238 lines
7.3 KiB
Texas Instruments eDMA |
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The eDMA3 consists of two components: Channel controller (CC) and Transfer |
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Controller(s) (TC). The CC is the main entry for DMA users since it is |
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responsible for the DMA channel handling, while the TCs are responsible to |
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execute the actual DMA tansfer. |
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------------------------------------------------------------------------------ |
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eDMA3 Channel Controller |
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Required properties: |
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-------------------- |
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- compatible: Should be: |
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- "ti,edma3-tpcc" for the channel controller(s) on OMAP, |
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AM33xx and AM43xx SoCs. |
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- "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the |
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channel controller(s) on 66AK2G. |
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- #dma-cells: Should be set to <2>. The first number is the DMA request |
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number and the second is the TC the channel is serviced on. |
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- reg: Memory map of eDMA CC |
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- reg-names: "edma3_cc" |
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- interrupts: Interrupt lines for CCINT, MPERR and CCERRINT. |
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- interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint" |
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- ti,tptcs: List of TPTCs associated with the eDMA in the following form: |
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<&tptc_phandle TC_priority_number>. The highest priority is 0. |
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SoC-specific Required properties: |
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-------------------------------- |
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The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only: |
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- ti,hwmods: Name of the hwmods associated to the eDMA CC. |
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The following are mandatory properties for 66AK2G SoCs only: |
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- power-domains:Should contain a phandle to a PM domain provider node |
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and an args specifier containing the device id |
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value. This property is as per the binding, |
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Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml |
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Optional properties: |
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------------------- |
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- ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow |
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these channels will be SW triggered channels. See example. |
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- ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by |
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the driver, they are allocated to be used by for example the |
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DSP. See example. |
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- dma-channel-mask: Mask of usable channels. |
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Single uint32 for EDMA with 32 channels, array of two uint32 for |
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EDMA with 64 channels. See example and |
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Documentation/devicetree/bindings/dma/dma-common.yaml |
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------------------------------------------------------------------------------ |
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eDMA3 Transfer Controller |
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Required properties: |
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-------------------- |
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- compatible: Should be: |
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- "ti,edma3-tptc" for the transfer controller(s) on OMAP, |
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AM33xx and AM43xx SoCs. |
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- "ti,k2g-edma3-tptc", "ti,edma3-tptc" for the |
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transfer controller(s) on 66AK2G. |
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- reg: Memory map of eDMA TC |
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- interrupts: Interrupt number for TCerrint. |
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SoC-specific Required properties: |
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-------------------------------- |
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The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only: |
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- ti,hwmods: Name of the hwmods associated to the eDMA TC. |
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The following are mandatory properties for 66AK2G SoCs only: |
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- power-domains:Should contain a phandle to a PM domain provider node |
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and an args specifier containing the device id |
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value. This property is as per the binding, |
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Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml |
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Optional properties: |
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------------------- |
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- interrupt-names: "edma3_tcerrint" |
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------------------------------------------------------------------------------ |
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Examples: |
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1. |
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edma: edma@49000000 { |
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compatible = "ti,edma3-tpcc"; |
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ti,hwmods = "tpcc"; |
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reg = <0x49000000 0x10000>; |
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reg-names = "edma3_cc"; |
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interrupts = <12 13 14>; |
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interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint"; |
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dma-requests = <64>; |
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#dma-cells = <2>; |
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ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>; |
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/* Channel 20 and 21 is allocated for memcpy */ |
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ti,edma-memcpy-channels = <20 21>; |
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/* The following PaRAM slots are reserved: 35-44 and 100-109 */ |
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ti,edma-reserved-slot-ranges = <35 10>, <100 10>; |
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/* The following channels are reserved: 35-44 */ |
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dma-channel-mask = <0xffffffff /* Channel 0-31 */ |
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0xffffe007>; /* Channel 32-63 */ |
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}; |
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edma_tptc0: tptc@49800000 { |
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compatible = "ti,edma3-tptc"; |
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ti,hwmods = "tptc0"; |
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reg = <0x49800000 0x100000>; |
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interrupts = <112>; |
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interrupt-names = "edm3_tcerrint"; |
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}; |
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edma_tptc1: tptc@49900000 { |
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compatible = "ti,edma3-tptc"; |
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ti,hwmods = "tptc1"; |
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reg = <0x49900000 0x100000>; |
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interrupts = <113>; |
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interrupt-names = "edm3_tcerrint"; |
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}; |
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edma_tptc2: tptc@49a00000 { |
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compatible = "ti,edma3-tptc"; |
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ti,hwmods = "tptc2"; |
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reg = <0x49a00000 0x100000>; |
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interrupts = <114>; |
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interrupt-names = "edm3_tcerrint"; |
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}; |
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sham: sham@53100000 { |
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compatible = "ti,omap4-sham"; |
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ti,hwmods = "sham"; |
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reg = <0x53100000 0x200>; |
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interrupts = <109>; |
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/* DMA channel 36 executed on eDMA TC0 - low priority queue */ |
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dmas = <&edma 36 0>; |
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dma-names = "rx"; |
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}; |
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mcasp0: mcasp@48038000 { |
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compatible = "ti,am33xx-mcasp-audio"; |
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ti,hwmods = "mcasp0"; |
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reg = <0x48038000 0x2000>, |
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<0x46000000 0x400000>; |
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reg-names = "mpu", "dat"; |
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interrupts = <80>, <81>; |
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interrupt-names = "tx", "rx"; |
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/* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */ |
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dmas = <&edma 8 2>, |
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<&edma 9 2>; |
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dma-names = "tx", "rx"; |
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}; |
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2. |
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edma1: edma@2728000 { |
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compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; |
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reg = <0x02728000 0x8000>; |
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reg-names = "edma3_cc"; |
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interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, |
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<GIC_SPI 219 IRQ_TYPE_EDGE_RISING>, |
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<GIC_SPI 220 IRQ_TYPE_EDGE_RISING>; |
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interrupt-names = "edma3_ccint", "emda3_mperr", |
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"edma3_ccerrint"; |
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dma-requests = <64>; |
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#dma-cells = <2>; |
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ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>; |
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/* |
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* memcpy is disabled, can be enabled with: |
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* ti,edma-memcpy-channels = <12 13 14 15>; |
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* for example. |
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*/ |
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power-domains = <&k2g_pds 0x4f>; |
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}; |
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edma1_tptc0: tptc@27b0000 { |
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compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; |
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reg = <0x027b0000 0x400>; |
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power-domains = <&k2g_pds 0x4f>; |
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}; |
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edma1_tptc1: tptc@27b8000 { |
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compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; |
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reg = <0x027b8000 0x400>; |
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power-domains = <&k2g_pds 0x4f>; |
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}; |
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mmc0: mmc@23000000 { |
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compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc"; |
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reg = <0x23000000 0x400>; |
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interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>; |
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dmas = <&edma1 24 0>, <&edma1 25 0>; |
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dma-names = "tx", "rx"; |
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bus-width = <4>; |
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ti,needs-special-reset; |
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no-1-8-v; |
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max-frequency = <96000000>; |
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power-domains = <&k2g_pds 0xb>; |
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clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>; |
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clock-names = "fck", "mmchsdb_fck"; |
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}; |
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------------------------------------------------------------------------------ |
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DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc |
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binding. |
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Required properties: |
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- compatible : "ti,edma3" |
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- #dma-cells: Should be set to <1> |
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Clients should use a single channel number per DMA request. |
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- reg: Memory map for accessing module |
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- interrupts: Exactly 3 interrupts need to be specified in the order: |
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1. Transfer completion interrupt. |
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2. Memory protection interrupt. |
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3. Error interrupt. |
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Optional properties: |
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- ti,hwmods: Name of the hwmods associated to the EDMA |
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- ti,edma-xbar-event-map: Crossbar event to channel map |
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Deprecated properties: |
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Listed here in case one wants to boot an old kernel with new DTB. These |
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properties might need to be added to the new DTS files. |
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- ti,edma-regions: Number of regions |
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- ti,edma-slots: Number of slots |
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- dma-channels: Specify total DMA channels per CC |
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Example: |
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edma: edma@49000000 { |
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reg = <0x49000000 0x10000>; |
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interrupt-parent = <&intc>; |
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interrupts = <12 13 14>; |
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compatible = "ti,edma3"; |
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ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; |
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#dma-cells = <1>; |
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ti,edma-xbar-event-map = /bits/ 16 <1 12 |
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2 13>; |
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};
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