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501 lines
15 KiB
501 lines
15 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* Copyright 2016-17 IBM Corp. |
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*/ |
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#ifndef _VAS_H |
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#define _VAS_H |
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#include <linux/atomic.h> |
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#include <linux/idr.h> |
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#include <asm/vas.h> |
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#include <linux/io.h> |
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#include <linux/dcache.h> |
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#include <linux/mutex.h> |
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#include <linux/stringify.h> |
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/* |
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* Overview of Virtual Accelerator Switchboard (VAS). |
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* |
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* VAS is a hardware "switchboard" that allows senders and receivers to |
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* exchange messages with _minimal_ kernel involvment. The receivers are |
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* typically NX coprocessor engines that perform compression or encryption |
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* in hardware, but receivers can also be other software threads. |
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* |
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* Senders are user/kernel threads that submit compression/encryption or |
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* other requests to the receivers. Senders must format their messages as |
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* Coprocessor Request Blocks (CRB)s and submit them using the "copy" and |
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* "paste" instructions which were introduced in Power9. |
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* |
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* A Power node can have (upto?) 8 Power chips. There is one instance of |
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* VAS in each Power9 chip. Each instance of VAS has 64K windows or ports, |
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* Senders and receivers must each connect to a separate window before they |
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* can exchange messages through the switchboard. |
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* |
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* Each window is described by two types of window contexts: |
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* |
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* Hypervisor Window Context (HVWC) of size VAS_HVWC_SIZE bytes |
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* |
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* OS/User Window Context (UWC) of size VAS_UWC_SIZE bytes. |
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* |
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* A window context can be viewed as a set of 64-bit registers. The settings |
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* in these registers configure/control/determine the behavior of the VAS |
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* hardware when messages are sent/received through the window. The registers |
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* in the HVWC are configured by the kernel while the registers in the UWC can |
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* be configured by the kernel or by the user space application that is using |
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* the window. |
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* |
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* The HVWCs for all windows on a specific instance of VAS are in a contiguous |
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* range of hardware addresses or Base address region (BAR) referred to as the |
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* HVWC BAR for the instance. Similarly the UWCs for all windows on an instance |
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* are referred to as the UWC BAR for the instance. |
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* |
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* The two BARs for each instance are defined Power9 MMIO Ranges spreadsheet |
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* and available to the kernel in the VAS node's "reg" property in the device |
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* tree: |
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* |
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* /proc/device-tree/vasm@.../reg |
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* |
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* (see vas_probe() for details on the reg property). |
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* |
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* The kernel maps the HVWC and UWC BAR regions into the kernel address |
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* space (hvwc_map and uwc_map). The kernel can then access the window |
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* contexts of a specific window using: |
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* |
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* hvwc = hvwc_map + winid * VAS_HVWC_SIZE. |
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* uwc = uwc_map + winid * VAS_UWC_SIZE. |
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* |
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* where winid is the window index (0..64K). |
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* |
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* As mentioned, a window context is used to "configure" a window. Besides |
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* this configuration address, each _send_ window also has a unique hardware |
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* "paste" address that is used to submit requests/CRBs (see vas_paste_crb()). |
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* |
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* The hardware paste address for a window is computed using the "paste |
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* base address" and "paste win id shift" reg properties in the VAS device |
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* tree node using: |
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* |
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* paste_addr = paste_base + ((winid << paste_win_id_shift)) |
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* |
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* (again, see vas_probe() for ->paste_base_addr and ->paste_win_id_shift). |
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* |
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* The kernel maps this hardware address into the sender's address space |
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* after which they can use the 'paste' instruction (new in Power9) to |
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* send a message (submit a request aka CRB) to the coprocessor. |
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* |
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* NOTE: In the initial version, senders can only in-kernel drivers/threads. |
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* Support for user space threads will be added in follow-on patches. |
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* |
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* TODO: Do we need to map the UWC into user address space so they can return |
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* credits? Its NA for NX but may be needed for other receive windows. |
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* |
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*/ |
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#define VAS_WINDOWS_PER_CHIP (64 << 10) |
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/* |
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* Hypervisor and OS/USer Window Context sizes |
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*/ |
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#define VAS_HVWC_SIZE 512 |
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#define VAS_UWC_SIZE PAGE_SIZE |
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/* |
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* Initial per-process credits. |
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* Max send window credits: 4K-1 (12-bits in VAS_TX_WCRED) |
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* |
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* TODO: Needs tuning for per-process credits |
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*/ |
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#define VAS_TX_WCREDS_MAX ((4 << 10) - 1) |
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#define VAS_WCREDS_DEFAULT (1 << 10) |
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/* |
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* VAS Window Context Register Offsets and bitmasks. |
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* See Section 3.1.4 of VAS Work book |
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*/ |
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#define VAS_LPID_OFFSET 0x010 |
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#define VAS_LPID PPC_BITMASK(0, 11) |
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#define VAS_PID_OFFSET 0x018 |
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#define VAS_PID_ID PPC_BITMASK(0, 19) |
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#define VAS_XLATE_MSR_OFFSET 0x020 |
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#define VAS_XLATE_MSR_DR PPC_BIT(0) |
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#define VAS_XLATE_MSR_TA PPC_BIT(1) |
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#define VAS_XLATE_MSR_PR PPC_BIT(2) |
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#define VAS_XLATE_MSR_US PPC_BIT(3) |
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#define VAS_XLATE_MSR_HV PPC_BIT(4) |
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#define VAS_XLATE_MSR_SF PPC_BIT(5) |
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#define VAS_XLATE_LPCR_OFFSET 0x028 |
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#define VAS_XLATE_LPCR_PAGE_SIZE PPC_BITMASK(0, 2) |
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#define VAS_XLATE_LPCR_ISL PPC_BIT(3) |
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#define VAS_XLATE_LPCR_TC PPC_BIT(4) |
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#define VAS_XLATE_LPCR_SC PPC_BIT(5) |
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#define VAS_XLATE_CTL_OFFSET 0x030 |
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#define VAS_XLATE_MODE PPC_BITMASK(0, 1) |
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#define VAS_AMR_OFFSET 0x040 |
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#define VAS_AMR PPC_BITMASK(0, 63) |
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#define VAS_SEIDR_OFFSET 0x048 |
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#define VAS_SEIDR PPC_BITMASK(0, 63) |
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#define VAS_FAULT_TX_WIN_OFFSET 0x050 |
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#define VAS_FAULT_TX_WIN PPC_BITMASK(48, 63) |
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#define VAS_OSU_INTR_SRC_RA_OFFSET 0x060 |
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#define VAS_OSU_INTR_SRC_RA PPC_BITMASK(8, 63) |
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#define VAS_HV_INTR_SRC_RA_OFFSET 0x070 |
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#define VAS_HV_INTR_SRC_RA PPC_BITMASK(8, 63) |
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#define VAS_PSWID_OFFSET 0x078 |
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#define VAS_PSWID_EA_HANDLE PPC_BITMASK(0, 31) |
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#define VAS_SPARE1_OFFSET 0x080 |
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#define VAS_SPARE2_OFFSET 0x088 |
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#define VAS_SPARE3_OFFSET 0x090 |
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#define VAS_SPARE4_OFFSET 0x130 |
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#define VAS_SPARE5_OFFSET 0x160 |
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#define VAS_SPARE6_OFFSET 0x188 |
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#define VAS_LFIFO_BAR_OFFSET 0x0A0 |
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#define VAS_LFIFO_BAR PPC_BITMASK(8, 53) |
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#define VAS_PAGE_MIGRATION_SELECT PPC_BITMASK(54, 56) |
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#define VAS_LDATA_STAMP_CTL_OFFSET 0x0A8 |
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#define VAS_LDATA_STAMP PPC_BITMASK(0, 1) |
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#define VAS_XTRA_WRITE PPC_BIT(2) |
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#define VAS_LDMA_CACHE_CTL_OFFSET 0x0B0 |
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#define VAS_LDMA_TYPE PPC_BITMASK(0, 1) |
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#define VAS_LDMA_FIFO_DISABLE PPC_BIT(2) |
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#define VAS_LRFIFO_PUSH_OFFSET 0x0B8 |
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#define VAS_LRFIFO_PUSH PPC_BITMASK(0, 15) |
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#define VAS_CURR_MSG_COUNT_OFFSET 0x0C0 |
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#define VAS_CURR_MSG_COUNT PPC_BITMASK(0, 7) |
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#define VAS_LNOTIFY_AFTER_COUNT_OFFSET 0x0C8 |
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#define VAS_LNOTIFY_AFTER_COUNT PPC_BITMASK(0, 7) |
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#define VAS_LRX_WCRED_OFFSET 0x0E0 |
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#define VAS_LRX_WCRED PPC_BITMASK(0, 15) |
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#define VAS_LRX_WCRED_ADDER_OFFSET 0x190 |
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#define VAS_LRX_WCRED_ADDER PPC_BITMASK(0, 15) |
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#define VAS_TX_WCRED_OFFSET 0x0F0 |
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#define VAS_TX_WCRED PPC_BITMASK(4, 15) |
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#define VAS_TX_WCRED_ADDER_OFFSET 0x1A0 |
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#define VAS_TX_WCRED_ADDER PPC_BITMASK(4, 15) |
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#define VAS_LFIFO_SIZE_OFFSET 0x100 |
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#define VAS_LFIFO_SIZE PPC_BITMASK(0, 3) |
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#define VAS_WINCTL_OFFSET 0x108 |
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#define VAS_WINCTL_OPEN PPC_BIT(0) |
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#define VAS_WINCTL_REJ_NO_CREDIT PPC_BIT(1) |
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#define VAS_WINCTL_PIN PPC_BIT(2) |
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#define VAS_WINCTL_TX_WCRED_MODE PPC_BIT(3) |
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#define VAS_WINCTL_RX_WCRED_MODE PPC_BIT(4) |
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#define VAS_WINCTL_TX_WORD_MODE PPC_BIT(5) |
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#define VAS_WINCTL_RX_WORD_MODE PPC_BIT(6) |
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#define VAS_WINCTL_RSVD_TXBUF PPC_BIT(7) |
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#define VAS_WINCTL_THRESH_CTL PPC_BITMASK(8, 9) |
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#define VAS_WINCTL_FAULT_WIN PPC_BIT(10) |
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#define VAS_WINCTL_NX_WIN PPC_BIT(11) |
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#define VAS_WIN_STATUS_OFFSET 0x110 |
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#define VAS_WIN_BUSY PPC_BIT(1) |
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#define VAS_WIN_CTX_CACHING_CTL_OFFSET 0x118 |
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#define VAS_CASTOUT_REQ PPC_BIT(0) |
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#define VAS_PUSH_TO_MEM PPC_BIT(1) |
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#define VAS_WIN_CACHE_STATUS PPC_BIT(4) |
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#define VAS_TX_RSVD_BUF_COUNT_OFFSET 0x120 |
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#define VAS_RXVD_BUF_COUNT PPC_BITMASK(58, 63) |
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#define VAS_LRFIFO_WIN_PTR_OFFSET 0x128 |
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#define VAS_LRX_WIN_ID PPC_BITMASK(0, 15) |
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/* |
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* Local Notification Control Register controls what happens in _response_ |
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* to a paste command and hence applies only to receive windows. |
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*/ |
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#define VAS_LNOTIFY_CTL_OFFSET 0x138 |
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#define VAS_NOTIFY_DISABLE PPC_BIT(0) |
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#define VAS_INTR_DISABLE PPC_BIT(1) |
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#define VAS_NOTIFY_EARLY PPC_BIT(2) |
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#define VAS_NOTIFY_OSU_INTR PPC_BIT(3) |
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#define VAS_LNOTIFY_PID_OFFSET 0x140 |
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#define VAS_LNOTIFY_PID PPC_BITMASK(0, 19) |
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#define VAS_LNOTIFY_LPID_OFFSET 0x148 |
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#define VAS_LNOTIFY_LPID PPC_BITMASK(0, 11) |
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#define VAS_LNOTIFY_TID_OFFSET 0x150 |
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#define VAS_LNOTIFY_TID PPC_BITMASK(0, 15) |
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#define VAS_LNOTIFY_SCOPE_OFFSET 0x158 |
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#define VAS_LNOTIFY_MIN_SCOPE PPC_BITMASK(0, 1) |
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#define VAS_LNOTIFY_MAX_SCOPE PPC_BITMASK(2, 3) |
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#define VAS_NX_UTIL_OFFSET 0x1B0 |
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#define VAS_NX_UTIL PPC_BITMASK(0, 63) |
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/* SE: Side effects */ |
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#define VAS_NX_UTIL_SE_OFFSET 0x1B8 |
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#define VAS_NX_UTIL_SE PPC_BITMASK(0, 63) |
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#define VAS_NX_UTIL_ADDER_OFFSET 0x180 |
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#define VAS_NX_UTIL_ADDER PPC_BITMASK(32, 63) |
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/* |
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* VREG(x): |
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* Expand a register's short name (eg: LPID) into two parameters: |
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* - the register's short name in string form ("LPID"), and |
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* - the name of the macro (eg: VAS_LPID_OFFSET), defining the |
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* register's offset in the window context |
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*/ |
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#define VREG_SFX(n, s) __stringify(n), VAS_##n##s |
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#define VREG(r) VREG_SFX(r, _OFFSET) |
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/* |
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* Local Notify Scope Control Register. (Receive windows only). |
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*/ |
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enum vas_notify_scope { |
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VAS_SCOPE_LOCAL, |
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VAS_SCOPE_GROUP, |
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VAS_SCOPE_VECTORED_GROUP, |
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VAS_SCOPE_UNUSED, |
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}; |
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/* |
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* Local DMA Cache Control Register (Receive windows only). |
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*/ |
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enum vas_dma_type { |
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VAS_DMA_TYPE_INJECT, |
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VAS_DMA_TYPE_WRITE, |
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}; |
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/* |
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* Local Notify Scope Control Register. (Receive windows only). |
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* Not applicable to NX receive windows. |
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*/ |
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enum vas_notify_after_count { |
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VAS_NOTIFY_AFTER_256 = 0, |
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VAS_NOTIFY_NONE, |
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VAS_NOTIFY_AFTER_2 |
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}; |
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/* |
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* NX can generate an interrupt for multiple faults and expects kernel |
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* to process all of them. So read all valid CRB entries until find the |
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* invalid one. So use pswid which is pasted by NX and ccw[0] (reserved |
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* bit in BE) to check valid CRB. CCW[0] will not be touched by user |
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* space. Application gets CRB formt error if it updates this bit. |
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* |
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* Invalidate FIFO during allocation and process all entries from last |
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* successful read until finds invalid pswid and ccw[0] values. |
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* After reading each CRB entry from fault FIFO, the kernel invalidate |
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* it by updating pswid with FIFO_INVALID_ENTRY and CCW[0] with |
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* CCW0_INVALID. |
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*/ |
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#define FIFO_INVALID_ENTRY 0xffffffff |
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#define CCW0_INVALID 1 |
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/* |
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* One per instance of VAS. Each instance will have a separate set of |
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* receive windows, one per coprocessor type. |
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* |
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* See also function header of set_vinst_win() for details on ->windows[] |
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* and ->rxwin[] tables. |
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*/ |
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struct vas_instance { |
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int vas_id; |
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struct ida ida; |
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struct list_head node; |
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struct platform_device *pdev; |
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u64 hvwc_bar_start; |
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u64 uwc_bar_start; |
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u64 paste_base_addr; |
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u64 paste_win_id_shift; |
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u64 irq_port; |
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int virq; |
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int fault_crbs; |
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int fault_fifo_size; |
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int fifo_in_progress; /* To wake up thread or return IRQ_HANDLED */ |
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spinlock_t fault_lock; /* Protects fifo_in_progress update */ |
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void *fault_fifo; |
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struct pnv_vas_window *fault_win; /* Fault window */ |
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struct mutex mutex; |
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struct pnv_vas_window *rxwin[VAS_COP_TYPE_MAX]; |
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struct pnv_vas_window *windows[VAS_WINDOWS_PER_CHIP]; |
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char *name; |
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char *dbgname; |
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struct dentry *dbgdir; |
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}; |
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/* |
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* In-kernel state a VAS window on PowerNV. One per window. |
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*/ |
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struct pnv_vas_window { |
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struct vas_window vas_win; |
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/* Fields common to send and receive windows */ |
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struct vas_instance *vinst; |
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bool tx_win; /* True if send window */ |
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bool nx_win; /* True if NX window */ |
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bool user_win; /* True if user space window */ |
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void *hvwc_map; /* HV window context */ |
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void *uwc_map; /* OS/User window context */ |
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/* Fields applicable only to send windows */ |
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void *paste_kaddr; |
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char *paste_addr_name; |
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struct pnv_vas_window *rxwin; |
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/* Fields applicable only to receive windows */ |
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atomic_t num_txwins; |
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}; |
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/* |
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* Container for the hardware state of a window. One per-window. |
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* |
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* A VAS Window context is a 512-byte area in the hardware that contains |
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* a set of 64-bit registers. Individual bit-fields in these registers |
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* determine the configuration/operation of the hardware. struct vas_winctx |
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* is a container for the register fields in the window context. |
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*/ |
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struct vas_winctx { |
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void *rx_fifo; |
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int rx_fifo_size; |
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int wcreds_max; |
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int rsvd_txbuf_count; |
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bool user_win; |
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bool nx_win; |
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bool fault_win; |
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bool rsvd_txbuf_enable; |
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bool pin_win; |
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bool rej_no_credit; |
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bool tx_wcred_mode; |
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bool rx_wcred_mode; |
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bool tx_word_mode; |
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bool rx_word_mode; |
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bool data_stamp; |
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bool xtra_write; |
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bool notify_disable; |
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bool intr_disable; |
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bool fifo_disable; |
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bool notify_early; |
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bool notify_os_intr_reg; |
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int lpid; |
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int pidr; /* value from SPRN_PID, not linux pid */ |
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int lnotify_lpid; |
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int lnotify_pid; |
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int lnotify_tid; |
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u32 pswid; |
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int rx_win_id; |
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int fault_win_id; |
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int tc_mode; |
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u64 irq_port; |
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enum vas_dma_type dma_type; |
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enum vas_notify_scope min_scope; |
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enum vas_notify_scope max_scope; |
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enum vas_notify_after_count notify_after_count; |
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}; |
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extern struct mutex vas_mutex; |
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extern struct vas_instance *find_vas_instance(int vasid); |
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extern void vas_init_dbgdir(void); |
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extern void vas_instance_init_dbgdir(struct vas_instance *vinst); |
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extern void vas_window_init_dbgdir(struct pnv_vas_window *win); |
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extern void vas_window_free_dbgdir(struct pnv_vas_window *win); |
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extern int vas_setup_fault_window(struct vas_instance *vinst); |
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extern irqreturn_t vas_fault_thread_fn(int irq, void *data); |
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extern irqreturn_t vas_fault_handler(int irq, void *dev_id); |
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extern void vas_return_credit(struct pnv_vas_window *window, bool tx); |
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extern struct pnv_vas_window *vas_pswid_to_window(struct vas_instance *vinst, |
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uint32_t pswid); |
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extern void vas_win_paste_addr(struct pnv_vas_window *window, u64 *addr, |
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int *len); |
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static inline int vas_window_pid(struct vas_window *window) |
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{ |
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return pid_vnr(window->task_ref.pid); |
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} |
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static inline void vas_log_write(struct pnv_vas_window *win, char *name, |
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void *regptr, u64 val) |
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{ |
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if (val) |
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pr_debug("%swin #%d: %s reg %p, val 0x%016llx\n", |
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win->tx_win ? "Tx" : "Rx", win->vas_win.winid, |
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name, regptr, val); |
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} |
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static inline void write_uwc_reg(struct pnv_vas_window *win, char *name, |
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s32 reg, u64 val) |
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{ |
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void *regptr; |
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regptr = win->uwc_map + reg; |
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vas_log_write(win, name, regptr, val); |
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out_be64(regptr, val); |
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} |
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static inline void write_hvwc_reg(struct pnv_vas_window *win, char *name, |
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s32 reg, u64 val) |
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{ |
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void *regptr; |
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regptr = win->hvwc_map + reg; |
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vas_log_write(win, name, regptr, val); |
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out_be64(regptr, val); |
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} |
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static inline u64 read_hvwc_reg(struct pnv_vas_window *win, |
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char *name __maybe_unused, s32 reg) |
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{ |
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return in_be64(win->hvwc_map+reg); |
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} |
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/* |
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* Encode/decode the Partition Send Window ID (PSWID) for a window in |
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* a way that we can uniquely identify any window in the system. i.e. |
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* we should be able to locate the 'struct vas_window' given the PSWID. |
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* |
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* Bits Usage |
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* 0:7 VAS id (8 bits) |
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* 8:15 Unused, 0 (3 bits) |
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* 16:31 Window id (16 bits) |
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*/ |
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static inline u32 encode_pswid(int vasid, int winid) |
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{ |
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return ((u32)winid | (vasid << (31 - 7))); |
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} |
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static inline void decode_pswid(u32 pswid, int *vasid, int *winid) |
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{ |
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if (vasid) |
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*vasid = pswid >> (31 - 7) & 0xFF; |
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if (winid) |
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*winid = pswid & 0xFFFF; |
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} |
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#endif /* _VAS_H */
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