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335 lines
8.5 KiB
335 lines
8.5 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* hw_ops.c - query/set operations on active SPU context. |
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* |
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* Copyright (C) IBM 2005 |
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* Author: Mark Nutter <[email protected]> |
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*/ |
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#include <linux/errno.h> |
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#include <linux/sched.h> |
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#include <linux/kernel.h> |
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#include <linux/mm.h> |
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#include <linux/poll.h> |
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#include <linux/smp.h> |
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#include <linux/stddef.h> |
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#include <linux/unistd.h> |
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#include <asm/io.h> |
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#include <asm/spu.h> |
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#include <asm/spu_priv1.h> |
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#include <asm/spu_csa.h> |
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#include <asm/mmu_context.h> |
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#include "spufs.h" |
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static int spu_hw_mbox_read(struct spu_context *ctx, u32 * data) |
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{ |
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struct spu *spu = ctx->spu; |
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struct spu_problem __iomem *prob = spu->problem; |
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u32 mbox_stat; |
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int ret = 0; |
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spin_lock_irq(&spu->register_lock); |
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mbox_stat = in_be32(&prob->mb_stat_R); |
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if (mbox_stat & 0x0000ff) { |
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*data = in_be32(&prob->pu_mb_R); |
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ret = 4; |
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} |
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spin_unlock_irq(&spu->register_lock); |
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return ret; |
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} |
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static u32 spu_hw_mbox_stat_read(struct spu_context *ctx) |
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{ |
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return in_be32(&ctx->spu->problem->mb_stat_R); |
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} |
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static __poll_t spu_hw_mbox_stat_poll(struct spu_context *ctx, __poll_t events) |
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{ |
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struct spu *spu = ctx->spu; |
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__poll_t ret = 0; |
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u32 stat; |
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spin_lock_irq(&spu->register_lock); |
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stat = in_be32(&spu->problem->mb_stat_R); |
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/* if the requested event is there, return the poll |
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mask, otherwise enable the interrupt to get notified, |
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but first mark any pending interrupts as done so |
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we don't get woken up unnecessarily */ |
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if (events & (EPOLLIN | EPOLLRDNORM)) { |
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if (stat & 0xff0000) |
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ret |= EPOLLIN | EPOLLRDNORM; |
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else { |
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spu_int_stat_clear(spu, 2, CLASS2_MAILBOX_INTR); |
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spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR); |
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} |
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} |
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if (events & (EPOLLOUT | EPOLLWRNORM)) { |
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if (stat & 0x00ff00) |
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ret = EPOLLOUT | EPOLLWRNORM; |
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else { |
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spu_int_stat_clear(spu, 2, |
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CLASS2_MAILBOX_THRESHOLD_INTR); |
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spu_int_mask_or(spu, 2, |
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CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR); |
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} |
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} |
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spin_unlock_irq(&spu->register_lock); |
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return ret; |
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} |
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static int spu_hw_ibox_read(struct spu_context *ctx, u32 * data) |
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{ |
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struct spu *spu = ctx->spu; |
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struct spu_problem __iomem *prob = spu->problem; |
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struct spu_priv2 __iomem *priv2 = spu->priv2; |
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int ret; |
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spin_lock_irq(&spu->register_lock); |
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if (in_be32(&prob->mb_stat_R) & 0xff0000) { |
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/* read the first available word */ |
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*data = in_be64(&priv2->puint_mb_R); |
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ret = 4; |
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} else { |
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/* make sure we get woken up by the interrupt */ |
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spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR); |
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ret = 0; |
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} |
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spin_unlock_irq(&spu->register_lock); |
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return ret; |
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} |
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static int spu_hw_wbox_write(struct spu_context *ctx, u32 data) |
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{ |
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struct spu *spu = ctx->spu; |
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struct spu_problem __iomem *prob = spu->problem; |
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int ret; |
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spin_lock_irq(&spu->register_lock); |
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if (in_be32(&prob->mb_stat_R) & 0x00ff00) { |
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/* we have space to write wbox_data to */ |
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out_be32(&prob->spu_mb_W, data); |
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ret = 4; |
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} else { |
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/* make sure we get woken up by the interrupt when space |
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becomes available */ |
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spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR); |
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ret = 0; |
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} |
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spin_unlock_irq(&spu->register_lock); |
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return ret; |
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} |
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static void spu_hw_signal1_write(struct spu_context *ctx, u32 data) |
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{ |
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out_be32(&ctx->spu->problem->signal_notify1, data); |
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} |
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static void spu_hw_signal2_write(struct spu_context *ctx, u32 data) |
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{ |
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out_be32(&ctx->spu->problem->signal_notify2, data); |
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} |
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static void spu_hw_signal1_type_set(struct spu_context *ctx, u64 val) |
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{ |
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struct spu *spu = ctx->spu; |
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struct spu_priv2 __iomem *priv2 = spu->priv2; |
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u64 tmp; |
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spin_lock_irq(&spu->register_lock); |
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tmp = in_be64(&priv2->spu_cfg_RW); |
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if (val) |
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tmp |= 1; |
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else |
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tmp &= ~1; |
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out_be64(&priv2->spu_cfg_RW, tmp); |
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spin_unlock_irq(&spu->register_lock); |
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} |
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static u64 spu_hw_signal1_type_get(struct spu_context *ctx) |
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{ |
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return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 1) != 0); |
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} |
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static void spu_hw_signal2_type_set(struct spu_context *ctx, u64 val) |
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{ |
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struct spu *spu = ctx->spu; |
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struct spu_priv2 __iomem *priv2 = spu->priv2; |
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u64 tmp; |
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spin_lock_irq(&spu->register_lock); |
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tmp = in_be64(&priv2->spu_cfg_RW); |
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if (val) |
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tmp |= 2; |
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else |
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tmp &= ~2; |
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out_be64(&priv2->spu_cfg_RW, tmp); |
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spin_unlock_irq(&spu->register_lock); |
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} |
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static u64 spu_hw_signal2_type_get(struct spu_context *ctx) |
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{ |
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return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 2) != 0); |
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} |
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static u32 spu_hw_npc_read(struct spu_context *ctx) |
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{ |
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return in_be32(&ctx->spu->problem->spu_npc_RW); |
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} |
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static void spu_hw_npc_write(struct spu_context *ctx, u32 val) |
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{ |
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out_be32(&ctx->spu->problem->spu_npc_RW, val); |
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} |
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static u32 spu_hw_status_read(struct spu_context *ctx) |
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{ |
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return in_be32(&ctx->spu->problem->spu_status_R); |
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} |
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static char *spu_hw_get_ls(struct spu_context *ctx) |
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{ |
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return ctx->spu->local_store; |
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} |
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static void spu_hw_privcntl_write(struct spu_context *ctx, u64 val) |
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{ |
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out_be64(&ctx->spu->priv2->spu_privcntl_RW, val); |
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} |
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static u32 spu_hw_runcntl_read(struct spu_context *ctx) |
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{ |
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return in_be32(&ctx->spu->problem->spu_runcntl_RW); |
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} |
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static void spu_hw_runcntl_write(struct spu_context *ctx, u32 val) |
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{ |
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spin_lock_irq(&ctx->spu->register_lock); |
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if (val & SPU_RUNCNTL_ISOLATE) |
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spu_hw_privcntl_write(ctx, |
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SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK); |
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out_be32(&ctx->spu->problem->spu_runcntl_RW, val); |
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spin_unlock_irq(&ctx->spu->register_lock); |
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} |
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static void spu_hw_runcntl_stop(struct spu_context *ctx) |
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{ |
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spin_lock_irq(&ctx->spu->register_lock); |
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out_be32(&ctx->spu->problem->spu_runcntl_RW, SPU_RUNCNTL_STOP); |
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while (in_be32(&ctx->spu->problem->spu_status_R) & SPU_STATUS_RUNNING) |
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cpu_relax(); |
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spin_unlock_irq(&ctx->spu->register_lock); |
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} |
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static void spu_hw_master_start(struct spu_context *ctx) |
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{ |
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struct spu *spu = ctx->spu; |
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u64 sr1; |
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spin_lock_irq(&spu->register_lock); |
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sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK; |
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spu_mfc_sr1_set(spu, sr1); |
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spin_unlock_irq(&spu->register_lock); |
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} |
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static void spu_hw_master_stop(struct spu_context *ctx) |
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{ |
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struct spu *spu = ctx->spu; |
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u64 sr1; |
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spin_lock_irq(&spu->register_lock); |
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sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; |
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spu_mfc_sr1_set(spu, sr1); |
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spin_unlock_irq(&spu->register_lock); |
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} |
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static int spu_hw_set_mfc_query(struct spu_context * ctx, u32 mask, u32 mode) |
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{ |
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struct spu_problem __iomem *prob = ctx->spu->problem; |
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int ret; |
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spin_lock_irq(&ctx->spu->register_lock); |
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ret = -EAGAIN; |
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if (in_be32(&prob->dma_querytype_RW)) |
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goto out; |
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ret = 0; |
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out_be32(&prob->dma_querymask_RW, mask); |
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out_be32(&prob->dma_querytype_RW, mode); |
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out: |
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spin_unlock_irq(&ctx->spu->register_lock); |
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return ret; |
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} |
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static u32 spu_hw_read_mfc_tagstatus(struct spu_context * ctx) |
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{ |
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return in_be32(&ctx->spu->problem->dma_tagstatus_R); |
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} |
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static u32 spu_hw_get_mfc_free_elements(struct spu_context *ctx) |
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{ |
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return in_be32(&ctx->spu->problem->dma_qstatus_R); |
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} |
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static int spu_hw_send_mfc_command(struct spu_context *ctx, |
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struct mfc_dma_command *cmd) |
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{ |
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u32 status; |
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struct spu_problem __iomem *prob = ctx->spu->problem; |
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spin_lock_irq(&ctx->spu->register_lock); |
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out_be32(&prob->mfc_lsa_W, cmd->lsa); |
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out_be64(&prob->mfc_ea_W, cmd->ea); |
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out_be32(&prob->mfc_union_W.by32.mfc_size_tag32, |
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cmd->size << 16 | cmd->tag); |
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out_be32(&prob->mfc_union_W.by32.mfc_class_cmd32, |
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cmd->class << 16 | cmd->cmd); |
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status = in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32); |
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spin_unlock_irq(&ctx->spu->register_lock); |
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switch (status & 0xffff) { |
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case 0: |
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return 0; |
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case 2: |
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return -EAGAIN; |
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default: |
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return -EINVAL; |
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} |
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} |
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static void spu_hw_restart_dma(struct spu_context *ctx) |
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{ |
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struct spu_priv2 __iomem *priv2 = ctx->spu->priv2; |
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if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &ctx->spu->flags)) |
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out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND); |
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} |
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struct spu_context_ops spu_hw_ops = { |
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.mbox_read = spu_hw_mbox_read, |
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.mbox_stat_read = spu_hw_mbox_stat_read, |
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.mbox_stat_poll = spu_hw_mbox_stat_poll, |
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.ibox_read = spu_hw_ibox_read, |
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.wbox_write = spu_hw_wbox_write, |
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.signal1_write = spu_hw_signal1_write, |
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.signal2_write = spu_hw_signal2_write, |
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.signal1_type_set = spu_hw_signal1_type_set, |
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.signal1_type_get = spu_hw_signal1_type_get, |
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.signal2_type_set = spu_hw_signal2_type_set, |
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.signal2_type_get = spu_hw_signal2_type_get, |
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.npc_read = spu_hw_npc_read, |
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.npc_write = spu_hw_npc_write, |
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.status_read = spu_hw_status_read, |
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.get_ls = spu_hw_get_ls, |
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.privcntl_write = spu_hw_privcntl_write, |
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.runcntl_read = spu_hw_runcntl_read, |
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.runcntl_write = spu_hw_runcntl_write, |
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.runcntl_stop = spu_hw_runcntl_stop, |
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.master_start = spu_hw_master_start, |
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.master_stop = spu_hw_master_stop, |
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.set_mfc_query = spu_hw_set_mfc_query, |
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.read_mfc_tagstatus = spu_hw_read_mfc_tagstatus, |
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.get_mfc_free_elements = spu_hw_get_mfc_free_elements, |
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.send_mfc_command = spu_hw_send_mfc_command, |
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.restart_dma = spu_hw_restart_dma, |
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};
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