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485 lines
11 KiB
485 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright 2007, Michael Ellerman, IBM Corporation. |
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*/ |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/kernel.h> |
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#include <linux/pci.h> |
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#include <linux/msi.h> |
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#include <linux/export.h> |
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#include <linux/of_platform.h> |
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#include <linux/slab.h> |
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#include <linux/debugfs.h> |
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#include <asm/dcr.h> |
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#include <asm/machdep.h> |
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#include <asm/prom.h> |
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#include "cell.h" |
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/* |
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* MSIC registers, specified as offsets from dcr_base |
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*/ |
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#define MSIC_CTRL_REG 0x0 |
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/* Base Address registers specify FIFO location in BE memory */ |
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#define MSIC_BASE_ADDR_HI_REG 0x3 |
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#define MSIC_BASE_ADDR_LO_REG 0x4 |
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/* Hold the read/write offsets into the FIFO */ |
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#define MSIC_READ_OFFSET_REG 0x5 |
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#define MSIC_WRITE_OFFSET_REG 0x6 |
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/* MSIC control register flags */ |
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#define MSIC_CTRL_ENABLE 0x0001 |
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#define MSIC_CTRL_FIFO_FULL_ENABLE 0x0002 |
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#define MSIC_CTRL_IRQ_ENABLE 0x0008 |
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#define MSIC_CTRL_FULL_STOP_ENABLE 0x0010 |
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/* |
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* The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB. |
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* Currently we're using a 64KB FIFO size. |
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*/ |
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#define MSIC_FIFO_SIZE_SHIFT 16 |
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#define MSIC_FIFO_SIZE_BYTES (1 << MSIC_FIFO_SIZE_SHIFT) |
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/* |
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* To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits |
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* 8-9 of the MSIC control reg. |
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*/ |
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#define MSIC_CTRL_FIFO_SIZE (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300) |
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/* |
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* We need to mask the read/write offsets to make sure they stay within |
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* the bounds of the FIFO. Also they should always be 16-byte aligned. |
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*/ |
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#define MSIC_FIFO_SIZE_MASK ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu) |
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/* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */ |
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#define MSIC_FIFO_ENTRY_SIZE 0x10 |
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struct axon_msic { |
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struct irq_domain *irq_domain; |
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__le32 *fifo_virt; |
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dma_addr_t fifo_phys; |
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dcr_host_t dcr_host; |
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u32 read_offset; |
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#ifdef DEBUG |
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u32 __iomem *trigger; |
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#endif |
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}; |
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#ifdef DEBUG |
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void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic); |
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#else |
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static inline void axon_msi_debug_setup(struct device_node *dn, |
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struct axon_msic *msic) { } |
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#endif |
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static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val) |
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{ |
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pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n); |
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dcr_write(msic->dcr_host, dcr_n, val); |
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} |
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static void axon_msi_cascade(struct irq_desc *desc) |
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{ |
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struct irq_chip *chip = irq_desc_get_chip(desc); |
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struct axon_msic *msic = irq_desc_get_handler_data(desc); |
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u32 write_offset, msi; |
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int idx; |
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int retry = 0; |
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write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG); |
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pr_devel("axon_msi: original write_offset 0x%x\n", write_offset); |
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/* write_offset doesn't wrap properly, so we have to mask it */ |
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write_offset &= MSIC_FIFO_SIZE_MASK; |
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while (msic->read_offset != write_offset && retry < 100) { |
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idx = msic->read_offset / sizeof(__le32); |
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msi = le32_to_cpu(msic->fifo_virt[idx]); |
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msi &= 0xFFFF; |
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pr_devel("axon_msi: woff %x roff %x msi %x\n", |
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write_offset, msic->read_offset, msi); |
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if (msi < nr_irqs && irq_get_chip_data(msi) == msic) { |
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generic_handle_irq(msi); |
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msic->fifo_virt[idx] = cpu_to_le32(0xffffffff); |
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} else { |
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/* |
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* Reading the MSIC_WRITE_OFFSET_REG does not |
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* reliably flush the outstanding DMA to the |
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* FIFO buffer. Here we were reading stale |
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* data, so we need to retry. |
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*/ |
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udelay(1); |
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retry++; |
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pr_devel("axon_msi: invalid irq 0x%x!\n", msi); |
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continue; |
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} |
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if (retry) { |
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pr_devel("axon_msi: late irq 0x%x, retry %d\n", |
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msi, retry); |
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retry = 0; |
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} |
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msic->read_offset += MSIC_FIFO_ENTRY_SIZE; |
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msic->read_offset &= MSIC_FIFO_SIZE_MASK; |
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} |
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if (retry) { |
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printk(KERN_WARNING "axon_msi: irq timed out\n"); |
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msic->read_offset += MSIC_FIFO_ENTRY_SIZE; |
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msic->read_offset &= MSIC_FIFO_SIZE_MASK; |
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} |
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chip->irq_eoi(&desc->irq_data); |
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} |
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static struct axon_msic *find_msi_translator(struct pci_dev *dev) |
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{ |
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struct irq_domain *irq_domain; |
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struct device_node *dn, *tmp; |
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const phandle *ph; |
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struct axon_msic *msic = NULL; |
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dn = of_node_get(pci_device_to_OF_node(dev)); |
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if (!dn) { |
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dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n"); |
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return NULL; |
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} |
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for (; dn; dn = of_get_next_parent(dn)) { |
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ph = of_get_property(dn, "msi-translator", NULL); |
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if (ph) |
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break; |
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} |
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if (!ph) { |
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dev_dbg(&dev->dev, |
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"axon_msi: no msi-translator property found\n"); |
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goto out_error; |
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} |
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tmp = dn; |
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dn = of_find_node_by_phandle(*ph); |
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of_node_put(tmp); |
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if (!dn) { |
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dev_dbg(&dev->dev, |
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"axon_msi: msi-translator doesn't point to a node\n"); |
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goto out_error; |
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} |
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irq_domain = irq_find_host(dn); |
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if (!irq_domain) { |
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dev_dbg(&dev->dev, "axon_msi: no irq_domain found for node %pOF\n", |
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dn); |
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goto out_error; |
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} |
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msic = irq_domain->host_data; |
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out_error: |
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of_node_put(dn); |
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return msic; |
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} |
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static int setup_msi_msg_address(struct pci_dev *dev, struct msi_msg *msg) |
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{ |
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struct device_node *dn; |
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struct msi_desc *entry; |
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int len; |
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const u32 *prop; |
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dn = of_node_get(pci_device_to_OF_node(dev)); |
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if (!dn) { |
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dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n"); |
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return -ENODEV; |
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} |
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entry = first_pci_msi_entry(dev); |
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for (; dn; dn = of_get_next_parent(dn)) { |
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if (entry->msi_attrib.is_64) { |
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prop = of_get_property(dn, "msi-address-64", &len); |
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if (prop) |
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break; |
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} |
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prop = of_get_property(dn, "msi-address-32", &len); |
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if (prop) |
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break; |
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} |
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if (!prop) { |
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dev_dbg(&dev->dev, |
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"axon_msi: no msi-address-(32|64) properties found\n"); |
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return -ENOENT; |
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} |
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switch (len) { |
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case 8: |
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msg->address_hi = prop[0]; |
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msg->address_lo = prop[1]; |
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break; |
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case 4: |
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msg->address_hi = 0; |
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msg->address_lo = prop[0]; |
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break; |
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default: |
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dev_dbg(&dev->dev, |
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"axon_msi: malformed msi-address-(32|64) property\n"); |
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of_node_put(dn); |
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return -EINVAL; |
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} |
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of_node_put(dn); |
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return 0; |
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} |
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static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
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{ |
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unsigned int virq, rc; |
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struct msi_desc *entry; |
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struct msi_msg msg; |
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struct axon_msic *msic; |
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msic = find_msi_translator(dev); |
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if (!msic) |
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return -ENODEV; |
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rc = setup_msi_msg_address(dev, &msg); |
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if (rc) |
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return rc; |
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for_each_pci_msi_entry(entry, dev) { |
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virq = irq_create_direct_mapping(msic->irq_domain); |
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if (!virq) { |
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dev_warn(&dev->dev, |
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"axon_msi: virq allocation failed!\n"); |
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return -1; |
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} |
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dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq); |
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irq_set_msi_desc(virq, entry); |
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msg.data = virq; |
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pci_write_msi_msg(virq, &msg); |
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} |
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return 0; |
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} |
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static void axon_msi_teardown_msi_irqs(struct pci_dev *dev) |
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{ |
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struct msi_desc *entry; |
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dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n"); |
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for_each_pci_msi_entry(entry, dev) { |
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if (!entry->irq) |
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continue; |
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irq_set_msi_desc(entry->irq, NULL); |
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irq_dispose_mapping(entry->irq); |
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} |
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} |
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static struct irq_chip msic_irq_chip = { |
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.irq_mask = pci_msi_mask_irq, |
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.irq_unmask = pci_msi_unmask_irq, |
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.irq_shutdown = pci_msi_mask_irq, |
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.name = "AXON-MSI", |
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}; |
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static int msic_host_map(struct irq_domain *h, unsigned int virq, |
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irq_hw_number_t hw) |
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{ |
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irq_set_chip_data(virq, h->host_data); |
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irq_set_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq); |
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return 0; |
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} |
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static const struct irq_domain_ops msic_host_ops = { |
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.map = msic_host_map, |
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}; |
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static void axon_msi_shutdown(struct platform_device *device) |
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{ |
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struct axon_msic *msic = dev_get_drvdata(&device->dev); |
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u32 tmp; |
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pr_devel("axon_msi: disabling %pOF\n", |
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irq_domain_get_of_node(msic->irq_domain)); |
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tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG); |
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tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE; |
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msic_dcr_write(msic, MSIC_CTRL_REG, tmp); |
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} |
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static int axon_msi_probe(struct platform_device *device) |
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{ |
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struct device_node *dn = device->dev.of_node; |
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struct axon_msic *msic; |
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unsigned int virq; |
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int dcr_base, dcr_len; |
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pr_devel("axon_msi: setting up dn %pOF\n", dn); |
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msic = kzalloc(sizeof(*msic), GFP_KERNEL); |
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if (!msic) { |
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printk(KERN_ERR "axon_msi: couldn't allocate msic for %pOF\n", |
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dn); |
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goto out; |
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} |
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dcr_base = dcr_resource_start(dn, 0); |
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dcr_len = dcr_resource_len(dn, 0); |
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if (dcr_base == 0 || dcr_len == 0) { |
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printk(KERN_ERR |
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"axon_msi: couldn't parse dcr properties on %pOF\n", |
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dn); |
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goto out_free_msic; |
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} |
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msic->dcr_host = dcr_map(dn, dcr_base, dcr_len); |
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if (!DCR_MAP_OK(msic->dcr_host)) { |
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printk(KERN_ERR "axon_msi: dcr_map failed for %pOF\n", |
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dn); |
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goto out_free_msic; |
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} |
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msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, |
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&msic->fifo_phys, GFP_KERNEL); |
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if (!msic->fifo_virt) { |
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printk(KERN_ERR "axon_msi: couldn't allocate fifo for %pOF\n", |
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dn); |
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goto out_free_msic; |
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} |
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virq = irq_of_parse_and_map(dn, 0); |
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if (!virq) { |
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printk(KERN_ERR "axon_msi: irq parse and map failed for %pOF\n", |
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dn); |
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goto out_free_fifo; |
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} |
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memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES); |
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/* We rely on being able to stash a virq in a u16, so limit irqs to < 65536 */ |
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msic->irq_domain = irq_domain_add_nomap(dn, 65536, &msic_host_ops, msic); |
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if (!msic->irq_domain) { |
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printk(KERN_ERR "axon_msi: couldn't allocate irq_domain for %pOF\n", |
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dn); |
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goto out_free_fifo; |
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} |
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irq_set_handler_data(virq, msic); |
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irq_set_chained_handler(virq, axon_msi_cascade); |
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pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq); |
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/* Enable the MSIC hardware */ |
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msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32); |
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msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG, |
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msic->fifo_phys & 0xFFFFFFFF); |
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msic_dcr_write(msic, MSIC_CTRL_REG, |
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MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE | |
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MSIC_CTRL_FIFO_SIZE); |
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msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG) |
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& MSIC_FIFO_SIZE_MASK; |
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dev_set_drvdata(&device->dev, msic); |
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cell_pci_controller_ops.setup_msi_irqs = axon_msi_setup_msi_irqs; |
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cell_pci_controller_ops.teardown_msi_irqs = axon_msi_teardown_msi_irqs; |
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axon_msi_debug_setup(dn, msic); |
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printk(KERN_DEBUG "axon_msi: setup MSIC on %pOF\n", dn); |
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return 0; |
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out_free_fifo: |
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dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt, |
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msic->fifo_phys); |
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out_free_msic: |
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kfree(msic); |
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out: |
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return -1; |
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} |
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static const struct of_device_id axon_msi_device_id[] = { |
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{ |
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.compatible = "ibm,axon-msic" |
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}, |
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{} |
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}; |
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static struct platform_driver axon_msi_driver = { |
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.probe = axon_msi_probe, |
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.shutdown = axon_msi_shutdown, |
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.driver = { |
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.name = "axon-msi", |
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.of_match_table = axon_msi_device_id, |
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}, |
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}; |
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static int __init axon_msi_init(void) |
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{ |
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return platform_driver_register(&axon_msi_driver); |
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} |
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subsys_initcall(axon_msi_init); |
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#ifdef DEBUG |
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static int msic_set(void *data, u64 val) |
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{ |
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struct axon_msic *msic = data; |
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out_le32(msic->trigger, val); |
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return 0; |
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} |
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static int msic_get(void *data, u64 *val) |
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{ |
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*val = 0; |
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return 0; |
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} |
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DEFINE_SIMPLE_ATTRIBUTE(fops_msic, msic_get, msic_set, "%llu\n"); |
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void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic) |
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{ |
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char name[8]; |
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u64 addr; |
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addr = of_translate_address(dn, of_get_property(dn, "reg", NULL)); |
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if (addr == OF_BAD_ADDR) { |
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pr_devel("axon_msi: couldn't translate reg property\n"); |
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return; |
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} |
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msic->trigger = ioremap(addr, 0x4); |
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if (!msic->trigger) { |
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pr_devel("axon_msi: ioremap failed\n"); |
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return; |
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} |
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snprintf(name, sizeof(name), "msic_%d", of_node_to_nid(dn)); |
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debugfs_create_file(name, 0600, arch_debugfs_dir, msic, &fops_msic); |
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} |
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#endif /* DEBUG */
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