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332 lines
8.7 KiB
332 lines
8.7 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* MPC8610 HPCD board specific routines |
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* |
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* Initial author: Xianghua Xiao <[email protected]> |
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* Recode: Jason Jin <[email protected]> |
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* York Sun <[email protected]> |
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* |
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* Rewrite the interrupt routing. remove the 8259PIC support, |
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* All the integrated device in ULI use sideband interrupt. |
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* |
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* Copyright 2008 Freescale Semiconductor Inc. |
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*/ |
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#include <linux/stddef.h> |
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#include <linux/kernel.h> |
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#include <linux/pci.h> |
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#include <linux/interrupt.h> |
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#include <linux/kdev_t.h> |
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#include <linux/delay.h> |
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#include <linux/seq_file.h> |
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#include <linux/of.h> |
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#include <linux/fsl/guts.h> |
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#include <asm/time.h> |
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#include <asm/machdep.h> |
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#include <asm/pci-bridge.h> |
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#include <asm/prom.h> |
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#include <mm/mmu_decl.h> |
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#include <asm/udbg.h> |
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#include <asm/mpic.h> |
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#include <linux/of_platform.h> |
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#include <sysdev/fsl_pci.h> |
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#include <sysdev/fsl_soc.h> |
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#include "mpc86xx.h" |
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static struct device_node *pixis_node; |
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static unsigned char *pixis_bdcfg0, *pixis_arch; |
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/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */ |
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#define CLKDVDR_PXCKEN 0x80000000 |
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#define CLKDVDR_PXCKINV 0x10000000 |
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#define CLKDVDR_PXCKDLY 0x06000000 |
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#define CLKDVDR_PXCLK_MASK 0x001F0000 |
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#ifdef CONFIG_SUSPEND |
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static irqreturn_t mpc8610_sw9_irq(int irq, void *data) |
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{ |
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pr_debug("%s: PIXIS' event (sw9/wakeup) IRQ handled\n", __func__); |
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return IRQ_HANDLED; |
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} |
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static void __init mpc8610_suspend_init(void) |
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{ |
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int irq; |
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int ret; |
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if (!pixis_node) |
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return; |
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irq = irq_of_parse_and_map(pixis_node, 0); |
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if (!irq) { |
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pr_err("%s: can't map pixis event IRQ.\n", __func__); |
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return; |
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} |
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ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9:wakeup", NULL); |
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if (ret) { |
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pr_err("%s: can't request pixis event IRQ: %d\n", |
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__func__, ret); |
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irq_dispose_mapping(irq); |
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} |
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enable_irq_wake(irq); |
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} |
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#else |
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static inline void mpc8610_suspend_init(void) { } |
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#endif /* CONFIG_SUSPEND */ |
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static const struct of_device_id mpc8610_ids[] __initconst = { |
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{ .compatible = "fsl,mpc8610-immr", }, |
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{ .compatible = "fsl,mpc8610-guts", }, |
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/* So that the DMA channel nodes can be probed individually: */ |
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{ .compatible = "fsl,eloplus-dma", }, |
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/* PCI controllers */ |
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{ .compatible = "fsl,mpc8610-pci", }, |
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{} |
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}; |
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static int __init mpc8610_declare_of_platform_devices(void) |
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{ |
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/* Enable wakeup on PIXIS' event IRQ. */ |
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mpc8610_suspend_init(); |
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mpc86xx_common_publish_devices(); |
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/* Without this call, the SSI device driver won't get probed. */ |
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of_platform_bus_probe(NULL, mpc8610_ids, NULL); |
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return 0; |
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} |
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machine_arch_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices); |
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) |
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/* |
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* DIU Area Descriptor |
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* |
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* The MPC8610 reference manual shows the bits of the AD register in |
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* little-endian order, which causes the BLUE_C field to be split into two |
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* parts. To simplify the definition of the MAKE_AD() macro, we define the |
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* fields in big-endian order and byte-swap the result. |
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* |
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* So even though the registers don't look like they're in the |
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* same bit positions as they are on the P1022, the same value is written to |
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* the AD register on the MPC8610 and on the P1022. |
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*/ |
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#define AD_BYTE_F 0x10000000 |
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#define AD_ALPHA_C_MASK 0x0E000000 |
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#define AD_ALPHA_C_SHIFT 25 |
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#define AD_BLUE_C_MASK 0x01800000 |
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#define AD_BLUE_C_SHIFT 23 |
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#define AD_GREEN_C_MASK 0x00600000 |
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#define AD_GREEN_C_SHIFT 21 |
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#define AD_RED_C_MASK 0x00180000 |
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#define AD_RED_C_SHIFT 19 |
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#define AD_PALETTE 0x00040000 |
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#define AD_PIXEL_S_MASK 0x00030000 |
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#define AD_PIXEL_S_SHIFT 16 |
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#define AD_COMP_3_MASK 0x0000F000 |
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#define AD_COMP_3_SHIFT 12 |
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#define AD_COMP_2_MASK 0x00000F00 |
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#define AD_COMP_2_SHIFT 8 |
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#define AD_COMP_1_MASK 0x000000F0 |
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#define AD_COMP_1_SHIFT 4 |
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#define AD_COMP_0_MASK 0x0000000F |
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#define AD_COMP_0_SHIFT 0 |
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#define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \ |
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cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \ |
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(blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \ |
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(red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \ |
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(c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \ |
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(c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT)) |
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u32 mpc8610hpcd_get_pixel_format(enum fsl_diu_monitor_port port, |
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unsigned int bits_per_pixel) |
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{ |
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static const u32 pixelformat[][3] = { |
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{ |
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MAKE_AD(3, 0, 2, 1, 3, 8, 8, 8, 8), |
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MAKE_AD(4, 2, 0, 1, 2, 8, 8, 8, 0), |
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MAKE_AD(4, 0, 2, 1, 1, 5, 6, 5, 0) |
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}, |
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{ |
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MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8), |
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MAKE_AD(4, 0, 2, 1, 2, 8, 8, 8, 0), |
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MAKE_AD(4, 2, 0, 1, 1, 5, 6, 5, 0) |
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}, |
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}; |
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unsigned int arch_monitor; |
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/* The DVI port is mis-wired on revision 1 of this board. */ |
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arch_monitor = |
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((*pixis_arch == 0x01) && (port == FSL_DIU_PORT_DVI)) ? 0 : 1; |
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switch (bits_per_pixel) { |
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case 32: |
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return pixelformat[arch_monitor][0]; |
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case 24: |
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return pixelformat[arch_monitor][1]; |
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case 16: |
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return pixelformat[arch_monitor][2]; |
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default: |
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pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel); |
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return 0; |
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} |
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} |
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void mpc8610hpcd_set_gamma_table(enum fsl_diu_monitor_port port, |
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char *gamma_table_base) |
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{ |
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int i; |
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if (port == FSL_DIU_PORT_DLVDS) { |
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for (i = 0; i < 256*3; i++) |
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gamma_table_base[i] = (gamma_table_base[i] << 2) | |
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((gamma_table_base[i] >> 6) & 0x03); |
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} |
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} |
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#define PX_BRDCFG0_DVISEL (1 << 3) |
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#define PX_BRDCFG0_DLINK (1 << 4) |
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#define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK) |
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void mpc8610hpcd_set_monitor_port(enum fsl_diu_monitor_port port) |
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{ |
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switch (port) { |
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case FSL_DIU_PORT_DVI: |
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clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK, |
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PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK); |
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break; |
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case FSL_DIU_PORT_LVDS: |
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clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK, |
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PX_BRDCFG0_DLINK); |
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break; |
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case FSL_DIU_PORT_DLVDS: |
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clrbits8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK); |
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break; |
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} |
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} |
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/** |
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* mpc8610hpcd_set_pixel_clock: program the DIU's clock |
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* |
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* @pixclock: the wavelength, in picoseconds, of the clock |
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*/ |
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void mpc8610hpcd_set_pixel_clock(unsigned int pixclock) |
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{ |
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struct device_node *guts_np = NULL; |
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struct ccsr_guts __iomem *guts; |
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unsigned long freq; |
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u64 temp; |
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u32 pxclk; |
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/* Map the global utilities registers. */ |
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guts_np = of_find_compatible_node(NULL, NULL, "fsl,mpc8610-guts"); |
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if (!guts_np) { |
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pr_err("mpc8610hpcd: missing global utilities device node\n"); |
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return; |
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} |
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guts = of_iomap(guts_np, 0); |
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of_node_put(guts_np); |
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if (!guts) { |
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pr_err("mpc8610hpcd: could not map global utilities device\n"); |
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return; |
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} |
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/* Convert pixclock from a wavelength to a frequency */ |
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temp = 1000000000000ULL; |
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do_div(temp, pixclock); |
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freq = temp; |
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/* |
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* 'pxclk' is the ratio of the platform clock to the pixel clock. |
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* On the MPC8610, the value programmed into CLKDVDR is the ratio |
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* minus one. The valid range of values is 2-31. |
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*/ |
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pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq) - 1; |
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pxclk = clamp_t(u32, pxclk, 2, 31); |
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/* Disable the pixel clock, and set it to non-inverted and no delay */ |
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clrbits32(&guts->clkdvdr, |
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CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK); |
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/* Enable the clock and set the pxclk */ |
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setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); |
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iounmap(guts); |
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} |
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enum fsl_diu_monitor_port |
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mpc8610hpcd_valid_monitor_port(enum fsl_diu_monitor_port port) |
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{ |
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return port; |
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} |
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#endif |
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static void __init mpc86xx_hpcd_setup_arch(void) |
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{ |
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struct resource r; |
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unsigned char *pixis; |
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if (ppc_md.progress) |
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ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0); |
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fsl_pci_assign_primary(); |
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) |
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diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format; |
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diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table; |
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diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port; |
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diu_ops.set_pixel_clock = mpc8610hpcd_set_pixel_clock; |
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diu_ops.valid_monitor_port = mpc8610hpcd_valid_monitor_port; |
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#endif |
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pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis"); |
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if (pixis_node) { |
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of_address_to_resource(pixis_node, 0, &r); |
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of_node_put(pixis_node); |
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pixis = ioremap(r.start, 32); |
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if (!pixis) { |
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printk(KERN_ERR "Err: can't map FPGA cfg register!\n"); |
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return; |
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} |
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pixis_bdcfg0 = pixis + 8; |
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pixis_arch = pixis + 1; |
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} else |
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printk(KERN_ERR "Err: " |
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"can't find device node 'fsl,fpga-pixis'\n"); |
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printk("MPC86xx HPCD board from Freescale Semiconductor\n"); |
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} |
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/* |
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* Called very early, device-tree isn't unflattened |
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*/ |
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static int __init mpc86xx_hpcd_probe(void) |
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{ |
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if (of_machine_is_compatible("fsl,MPC8610HPCD")) |
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return 1; /* Looks good */ |
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return 0; |
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} |
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define_machine(mpc86xx_hpcd) { |
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.name = "MPC86xx HPCD", |
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.probe = mpc86xx_hpcd_probe, |
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.setup_arch = mpc86xx_hpcd_setup_arch, |
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.init_IRQ = mpc86xx_init_irq, |
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.get_irq = mpic_get_irq, |
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.time_init = mpc86xx_time_init, |
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.calibrate_decr = generic_calibrate_decr, |
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.progress = udbg_progress, |
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#ifdef CONFIG_PCI |
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
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#endif |
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};
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