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197 lines
4.8 KiB
197 lines
4.8 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2009 Extreme Engineering Solutions, Inc. |
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* |
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* X-ES board-specific functionality |
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* |
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* Based on mpc85xx_ds code from Freescale Semiconductor, Inc. |
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* |
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* Author: Nate Case <[email protected]> |
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*/ |
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#include <linux/stddef.h> |
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#include <linux/kernel.h> |
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#include <linux/pci.h> |
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#include <linux/kdev_t.h> |
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#include <linux/delay.h> |
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#include <linux/seq_file.h> |
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#include <linux/interrupt.h> |
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#include <linux/of_platform.h> |
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#include <asm/time.h> |
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#include <asm/machdep.h> |
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#include <asm/pci-bridge.h> |
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#include <mm/mmu_decl.h> |
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#include <asm/prom.h> |
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#include <asm/udbg.h> |
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#include <asm/mpic.h> |
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#include <sysdev/fsl_soc.h> |
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#include <sysdev/fsl_pci.h> |
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#include "smp.h" |
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#include "mpc85xx.h" |
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/* A few bit definitions needed for fixups on some boards */ |
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#define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */ |
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#define MPC85xx_L2CTL_L2I 0x40000000 /* L2 flash invalidate */ |
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#define MPC85xx_L2CTL_L2SIZ_MASK 0x30000000 /* L2 SRAM size (R/O) */ |
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void __init xes_mpc85xx_pic_init(void) |
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{ |
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struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN, |
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0, 256, " OpenPIC "); |
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BUG_ON(mpic == NULL); |
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mpic_init(mpic); |
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} |
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static void xes_mpc85xx_configure_l2(void __iomem *l2_base) |
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{ |
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volatile uint32_t ctl, tmp; |
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asm volatile("msync; isync"); |
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tmp = in_be32(l2_base); |
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/* |
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* xMon may have enabled part of L2 as SRAM, so we need to set it |
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* up for all cache mode just to be safe. |
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*/ |
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printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n"); |
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ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I; |
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if (of_machine_is_compatible("MPC8540") || |
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of_machine_is_compatible("MPC8560")) |
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/* |
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* Assume L2 SRAM is used fully for cache, so set |
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* L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3). |
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*/ |
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ctl |= (tmp & MPC85xx_L2CTL_L2SIZ_MASK) >> 2; |
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asm volatile("msync; isync"); |
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out_be32(l2_base, ctl); |
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asm volatile("msync; isync"); |
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} |
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static void xes_mpc85xx_fixups(void) |
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{ |
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struct device_node *np; |
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int err; |
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/* |
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* Legacy xMon firmware on some X-ES boards does not enable L2 |
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* as cache. We must ensure that they get enabled here. |
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*/ |
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for_each_node_by_name(np, "l2-cache-controller") { |
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struct resource r[2]; |
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void __iomem *l2_base; |
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/* Only MPC8548, MPC8540, and MPC8560 boards are affected */ |
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if (!of_device_is_compatible(np, |
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"fsl,mpc8548-l2-cache-controller") && |
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!of_device_is_compatible(np, |
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"fsl,mpc8540-l2-cache-controller") && |
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!of_device_is_compatible(np, |
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"fsl,mpc8560-l2-cache-controller")) |
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continue; |
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err = of_address_to_resource(np, 0, &r[0]); |
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if (err) { |
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printk(KERN_WARNING "xes_mpc85xx: Could not get " |
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"resource for device tree node '%pOF'", |
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np); |
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continue; |
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} |
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l2_base = ioremap(r[0].start, resource_size(&r[0])); |
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xes_mpc85xx_configure_l2(l2_base); |
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} |
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} |
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/* |
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* Setup the architecture |
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*/ |
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static void __init xes_mpc85xx_setup_arch(void) |
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{ |
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struct device_node *root; |
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const char *model = "Unknown"; |
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root = of_find_node_by_path("/"); |
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if (root == NULL) |
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return; |
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model = of_get_property(root, "model", NULL); |
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printk(KERN_INFO "X-ES MPC85xx-based single-board computer: %s\n", |
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model + strlen("xes,")); |
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xes_mpc85xx_fixups(); |
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mpc85xx_smp_init(); |
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fsl_pci_assign_primary(); |
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} |
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machine_arch_initcall(xes_mpc8572, mpc85xx_common_publish_devices); |
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machine_arch_initcall(xes_mpc8548, mpc85xx_common_publish_devices); |
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machine_arch_initcall(xes_mpc8540, mpc85xx_common_publish_devices); |
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/* |
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* Called very early, device-tree isn't unflattened |
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*/ |
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static int __init xes_mpc8572_probe(void) |
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{ |
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return of_machine_is_compatible("xes,MPC8572"); |
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} |
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static int __init xes_mpc8548_probe(void) |
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{ |
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return of_machine_is_compatible("xes,MPC8548"); |
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} |
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static int __init xes_mpc8540_probe(void) |
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{ |
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return of_machine_is_compatible("xes,MPC8540"); |
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} |
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define_machine(xes_mpc8572) { |
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.name = "X-ES MPC8572", |
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.probe = xes_mpc8572_probe, |
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.setup_arch = xes_mpc85xx_setup_arch, |
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.init_IRQ = xes_mpc85xx_pic_init, |
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#ifdef CONFIG_PCI |
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb, |
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#endif |
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.get_irq = mpic_get_irq, |
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.calibrate_decr = generic_calibrate_decr, |
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.progress = udbg_progress, |
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}; |
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define_machine(xes_mpc8548) { |
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.name = "X-ES MPC8548", |
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.probe = xes_mpc8548_probe, |
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.setup_arch = xes_mpc85xx_setup_arch, |
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.init_IRQ = xes_mpc85xx_pic_init, |
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#ifdef CONFIG_PCI |
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb, |
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#endif |
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.get_irq = mpic_get_irq, |
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.calibrate_decr = generic_calibrate_decr, |
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.progress = udbg_progress, |
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}; |
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define_machine(xes_mpc8540) { |
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.name = "X-ES MPC8540", |
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.probe = xes_mpc8540_probe, |
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.setup_arch = xes_mpc85xx_setup_arch, |
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.init_IRQ = xes_mpc85xx_pic_init, |
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#ifdef CONFIG_PCI |
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb, |
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#endif |
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.get_irq = mpic_get_irq, |
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.calibrate_decr = generic_calibrate_decr, |
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.progress = udbg_progress, |
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};
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