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214 lines
4.7 KiB
214 lines
4.7 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* GE IMP3A Board Setup |
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* |
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* Author Martyn Welch <[email protected]> |
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* |
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* Copyright 2010 GE Intelligent Platforms Embedded Systems, Inc. |
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* |
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* Based on: mpc85xx_ds.c (MPC85xx DS Board Setup) |
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* Copyright 2007 Freescale Semiconductor Inc. |
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*/ |
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#include <linux/stddef.h> |
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#include <linux/kernel.h> |
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#include <linux/pci.h> |
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#include <linux/kdev_t.h> |
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#include <linux/delay.h> |
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#include <linux/seq_file.h> |
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#include <linux/interrupt.h> |
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#include <linux/of_platform.h> |
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#include <asm/time.h> |
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#include <asm/machdep.h> |
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#include <asm/pci-bridge.h> |
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#include <mm/mmu_decl.h> |
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#include <asm/prom.h> |
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#include <asm/udbg.h> |
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#include <asm/mpic.h> |
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#include <asm/swiotlb.h> |
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#include <asm/nvram.h> |
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#include <sysdev/fsl_soc.h> |
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#include <sysdev/fsl_pci.h> |
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#include "smp.h" |
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#include "mpc85xx.h" |
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#include <sysdev/ge/ge_pic.h> |
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void __iomem *imp3a_regs; |
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void __init ge_imp3a_pic_init(void) |
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{ |
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struct mpic *mpic; |
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struct device_node *np; |
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struct device_node *cascade_node = NULL; |
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if (of_machine_is_compatible("fsl,MPC8572DS-CAMP")) { |
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mpic = mpic_alloc(NULL, 0, |
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MPIC_NO_RESET | |
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MPIC_BIG_ENDIAN | |
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MPIC_SINGLE_DEST_CPU, |
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0, 256, " OpenPIC "); |
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} else { |
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mpic = mpic_alloc(NULL, 0, |
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MPIC_BIG_ENDIAN | |
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MPIC_SINGLE_DEST_CPU, |
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0, 256, " OpenPIC "); |
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} |
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BUG_ON(mpic == NULL); |
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mpic_init(mpic); |
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/* |
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* There is a simple interrupt handler in the main FPGA, this needs |
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* to be cascaded into the MPIC |
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*/ |
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for_each_node_by_type(np, "interrupt-controller") |
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if (of_device_is_compatible(np, "gef,fpga-pic-1.00")) { |
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cascade_node = np; |
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break; |
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} |
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if (cascade_node == NULL) { |
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printk(KERN_WARNING "IMP3A: No FPGA PIC\n"); |
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return; |
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} |
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gef_pic_init(cascade_node); |
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of_node_put(cascade_node); |
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} |
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static void ge_imp3a_pci_assign_primary(void) |
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{ |
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#ifdef CONFIG_PCI |
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struct device_node *np; |
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struct resource rsrc; |
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for_each_node_by_type(np, "pci") { |
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if (of_device_is_compatible(np, "fsl,mpc8540-pci") || |
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of_device_is_compatible(np, "fsl,mpc8548-pcie") || |
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of_device_is_compatible(np, "fsl,p2020-pcie")) { |
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of_address_to_resource(np, 0, &rsrc); |
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if ((rsrc.start & 0xfffff) == 0x9000) |
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fsl_pci_primary = np; |
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} |
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} |
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#endif |
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} |
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/* |
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* Setup the architecture |
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*/ |
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static void __init ge_imp3a_setup_arch(void) |
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{ |
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struct device_node *regs; |
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if (ppc_md.progress) |
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ppc_md.progress("ge_imp3a_setup_arch()", 0); |
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mpc85xx_smp_init(); |
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ge_imp3a_pci_assign_primary(); |
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swiotlb_detect_4g(); |
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/* Remap basic board registers */ |
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regs = of_find_compatible_node(NULL, NULL, "ge,imp3a-fpga-regs"); |
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if (regs) { |
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imp3a_regs = of_iomap(regs, 0); |
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if (imp3a_regs == NULL) |
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printk(KERN_WARNING "Unable to map board registers\n"); |
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of_node_put(regs); |
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} |
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#if defined(CONFIG_MMIO_NVRAM) |
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mmio_nvram_init(); |
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#endif |
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printk(KERN_INFO "GE Intelligent Platforms IMP3A 3U cPCI SBC\n"); |
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} |
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/* Return the PCB revision */ |
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static unsigned int ge_imp3a_get_pcb_rev(void) |
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{ |
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unsigned int reg; |
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reg = ioread16(imp3a_regs); |
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return (reg >> 8) & 0xff; |
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} |
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/* Return the board (software) revision */ |
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static unsigned int ge_imp3a_get_board_rev(void) |
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{ |
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unsigned int reg; |
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reg = ioread16(imp3a_regs + 0x2); |
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return reg & 0xff; |
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} |
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/* Return the FPGA revision */ |
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static unsigned int ge_imp3a_get_fpga_rev(void) |
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{ |
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unsigned int reg; |
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reg = ioread16(imp3a_regs + 0x2); |
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return (reg >> 8) & 0xff; |
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} |
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/* Return compactPCI Geographical Address */ |
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static unsigned int ge_imp3a_get_cpci_geo_addr(void) |
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{ |
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unsigned int reg; |
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reg = ioread16(imp3a_regs + 0x6); |
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return (reg & 0x0f00) >> 8; |
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} |
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/* Return compactPCI System Controller Status */ |
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static unsigned int ge_imp3a_get_cpci_is_syscon(void) |
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{ |
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unsigned int reg; |
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reg = ioread16(imp3a_regs + 0x6); |
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return reg & (1 << 12); |
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} |
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static void ge_imp3a_show_cpuinfo(struct seq_file *m) |
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{ |
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seq_printf(m, "Vendor\t\t: GE Intelligent Platforms\n"); |
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seq_printf(m, "Revision\t: %u%c\n", ge_imp3a_get_pcb_rev(), |
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('A' + ge_imp3a_get_board_rev() - 1)); |
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seq_printf(m, "FPGA Revision\t: %u\n", ge_imp3a_get_fpga_rev()); |
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seq_printf(m, "cPCI geo. addr\t: %u\n", ge_imp3a_get_cpci_geo_addr()); |
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seq_printf(m, "cPCI syscon\t: %s\n", |
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ge_imp3a_get_cpci_is_syscon() ? "yes" : "no"); |
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} |
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/* |
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* Called very early, device-tree isn't unflattened |
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*/ |
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static int __init ge_imp3a_probe(void) |
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{ |
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return of_machine_is_compatible("ge,IMP3A"); |
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} |
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machine_arch_initcall(ge_imp3a, mpc85xx_common_publish_devices); |
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define_machine(ge_imp3a) { |
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.name = "GE_IMP3A", |
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.probe = ge_imp3a_probe, |
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.setup_arch = ge_imp3a_setup_arch, |
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.init_IRQ = ge_imp3a_pic_init, |
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.show_cpuinfo = ge_imp3a_show_cpuinfo, |
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#ifdef CONFIG_PCI |
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb, |
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#endif |
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.get_irq = mpic_get_irq, |
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.calibrate_decr = generic_calibrate_decr, |
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.progress = udbg_progress, |
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};
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