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251 lines
6.5 KiB
251 lines
6.5 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Freescale 83xx USB SOC setup code |
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* |
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* Copyright (C) 2007 Freescale Semiconductor, Inc. |
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* Author: Li Yang |
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*/ |
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#include <linux/stddef.h> |
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#include <linux/kernel.h> |
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#include <linux/errno.h> |
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#include <linux/of.h> |
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#include <asm/io.h> |
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#include <asm/prom.h> |
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#include <sysdev/fsl_soc.h> |
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#include "mpc83xx.h" |
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#ifdef CONFIG_PPC_MPC834x |
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int mpc834x_usb_cfg(void) |
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{ |
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unsigned long sccr, sicrl, sicrh; |
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void __iomem *immap; |
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struct device_node *np = NULL; |
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int port0_is_dr = 0, port1_is_dr = 0; |
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const void *prop, *dr_mode; |
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immap = ioremap(get_immrbase(), 0x1000); |
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if (!immap) |
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return -ENOMEM; |
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/* Read registers */ |
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/* Note: DR and MPH must use the same clock setting in SCCR */ |
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sccr = in_be32(immap + MPC83XX_SCCR_OFFS) & ~MPC83XX_SCCR_USB_MASK; |
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sicrl = in_be32(immap + MPC83XX_SICRL_OFFS) & ~MPC834X_SICRL_USB_MASK; |
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sicrh = in_be32(immap + MPC83XX_SICRH_OFFS) & ~MPC834X_SICRH_USB_UTMI; |
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np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr"); |
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if (np) { |
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sccr |= MPC83XX_SCCR_USB_DRCM_11; /* 1:3 */ |
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prop = of_get_property(np, "phy_type", NULL); |
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port1_is_dr = 1; |
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if (prop && (!strcmp(prop, "utmi") || |
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!strcmp(prop, "utmi_wide"))) { |
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sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1; |
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sicrh |= MPC834X_SICRH_USB_UTMI; |
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port0_is_dr = 1; |
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} else if (prop && !strcmp(prop, "serial")) { |
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dr_mode = of_get_property(np, "dr_mode", NULL); |
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if (dr_mode && !strcmp(dr_mode, "otg")) { |
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sicrl |= MPC834X_SICRL_USB0 | MPC834X_SICRL_USB1; |
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port0_is_dr = 1; |
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} else { |
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sicrl |= MPC834X_SICRL_USB1; |
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} |
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} else if (prop && !strcmp(prop, "ulpi")) { |
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sicrl |= MPC834X_SICRL_USB1; |
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} else { |
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printk(KERN_WARNING "834x USB PHY type not supported\n"); |
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} |
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of_node_put(np); |
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} |
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np = of_find_compatible_node(NULL, NULL, "fsl-usb2-mph"); |
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if (np) { |
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sccr |= MPC83XX_SCCR_USB_MPHCM_11; /* 1:3 */ |
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prop = of_get_property(np, "port0", NULL); |
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if (prop) { |
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if (port0_is_dr) |
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printk(KERN_WARNING |
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"834x USB port0 can't be used by both DR and MPH!\n"); |
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sicrl &= ~MPC834X_SICRL_USB0; |
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} |
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prop = of_get_property(np, "port1", NULL); |
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if (prop) { |
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if (port1_is_dr) |
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printk(KERN_WARNING |
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"834x USB port1 can't be used by both DR and MPH!\n"); |
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sicrl &= ~MPC834X_SICRL_USB1; |
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} |
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of_node_put(np); |
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} |
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/* Write back */ |
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out_be32(immap + MPC83XX_SCCR_OFFS, sccr); |
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out_be32(immap + MPC83XX_SICRL_OFFS, sicrl); |
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out_be32(immap + MPC83XX_SICRH_OFFS, sicrh); |
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iounmap(immap); |
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return 0; |
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} |
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#endif /* CONFIG_PPC_MPC834x */ |
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#ifdef CONFIG_PPC_MPC831x |
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int mpc831x_usb_cfg(void) |
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{ |
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u32 temp; |
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void __iomem *immap, *usb_regs; |
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struct device_node *np = NULL; |
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struct device_node *immr_node = NULL; |
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const void *prop; |
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struct resource res; |
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int ret = 0; |
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#ifdef CONFIG_USB_OTG |
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const void *dr_mode; |
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#endif |
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np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr"); |
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if (!np) |
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return -ENODEV; |
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prop = of_get_property(np, "phy_type", NULL); |
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/* Map IMMR space for pin and clock settings */ |
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immap = ioremap(get_immrbase(), 0x1000); |
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if (!immap) { |
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of_node_put(np); |
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return -ENOMEM; |
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} |
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/* Configure clock */ |
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immr_node = of_get_parent(np); |
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if (immr_node && (of_device_is_compatible(immr_node, "fsl,mpc8315-immr") || |
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of_device_is_compatible(immr_node, "fsl,mpc8308-immr"))) |
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clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, |
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MPC8315_SCCR_USB_MASK, |
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MPC8315_SCCR_USB_DRCM_01); |
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else |
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clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, |
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MPC83XX_SCCR_USB_MASK, |
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MPC83XX_SCCR_USB_DRCM_11); |
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/* Configure pin mux for ULPI. There is no pin mux for UTMI */ |
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if (prop && !strcmp(prop, "ulpi")) { |
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if (of_device_is_compatible(immr_node, "fsl,mpc8308-immr")) { |
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clrsetbits_be32(immap + MPC83XX_SICRH_OFFS, |
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MPC8308_SICRH_USB_MASK, |
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MPC8308_SICRH_USB_ULPI); |
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} else if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr")) { |
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clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, |
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MPC8315_SICRL_USB_MASK, |
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MPC8315_SICRL_USB_ULPI); |
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clrsetbits_be32(immap + MPC83XX_SICRH_OFFS, |
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MPC8315_SICRH_USB_MASK, |
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MPC8315_SICRH_USB_ULPI); |
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} else { |
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clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, |
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MPC831X_SICRL_USB_MASK, |
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MPC831X_SICRL_USB_ULPI); |
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clrsetbits_be32(immap + MPC83XX_SICRH_OFFS, |
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MPC831X_SICRH_USB_MASK, |
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MPC831X_SICRH_USB_ULPI); |
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} |
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} |
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iounmap(immap); |
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of_node_put(immr_node); |
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/* Map USB SOC space */ |
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ret = of_address_to_resource(np, 0, &res); |
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if (ret) { |
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of_node_put(np); |
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return ret; |
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} |
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usb_regs = ioremap(res.start, resource_size(&res)); |
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/* Using on-chip PHY */ |
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if (prop && (!strcmp(prop, "utmi_wide") || |
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!strcmp(prop, "utmi"))) { |
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u32 refsel; |
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if (of_device_is_compatible(immr_node, "fsl,mpc8308-immr")) |
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goto out; |
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if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr")) |
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refsel = CONTROL_REFSEL_24MHZ; |
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else |
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refsel = CONTROL_REFSEL_48MHZ; |
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/* Set UTMI_PHY_EN and REFSEL */ |
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out_be32(usb_regs + FSL_USB2_CONTROL_OFFS, |
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CONTROL_UTMI_PHY_EN | refsel); |
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/* Using external UPLI PHY */ |
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} else if (prop && !strcmp(prop, "ulpi")) { |
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/* Set PHY_CLK_SEL to ULPI */ |
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temp = CONTROL_PHY_CLK_SEL_ULPI; |
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#ifdef CONFIG_USB_OTG |
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/* Set OTG_PORT */ |
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if (!of_device_is_compatible(immr_node, "fsl,mpc8308-immr")) { |
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dr_mode = of_get_property(np, "dr_mode", NULL); |
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if (dr_mode && !strcmp(dr_mode, "otg")) |
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temp |= CONTROL_OTG_PORT; |
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} |
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#endif /* CONFIG_USB_OTG */ |
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out_be32(usb_regs + FSL_USB2_CONTROL_OFFS, temp); |
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} else { |
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printk(KERN_WARNING "831x USB PHY type not supported\n"); |
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ret = -EINVAL; |
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} |
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out: |
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iounmap(usb_regs); |
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of_node_put(np); |
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return ret; |
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} |
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#endif /* CONFIG_PPC_MPC831x */ |
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#ifdef CONFIG_PPC_MPC837x |
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int mpc837x_usb_cfg(void) |
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{ |
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void __iomem *immap; |
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struct device_node *np = NULL; |
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const void *prop; |
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int ret = 0; |
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np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr"); |
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if (!np || !of_device_is_available(np)) { |
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of_node_put(np); |
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return -ENODEV; |
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} |
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prop = of_get_property(np, "phy_type", NULL); |
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if (!prop || (strcmp(prop, "ulpi") && strcmp(prop, "serial"))) { |
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printk(KERN_WARNING "837x USB PHY type not supported\n"); |
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of_node_put(np); |
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return -EINVAL; |
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} |
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/* Map IMMR space for pin and clock settings */ |
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immap = ioremap(get_immrbase(), 0x1000); |
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if (!immap) { |
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of_node_put(np); |
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return -ENOMEM; |
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} |
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/* Configure clock */ |
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clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, MPC837X_SCCR_USB_DRCM_11, |
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MPC837X_SCCR_USB_DRCM_11); |
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/* Configure pin mux for ULPI/serial */ |
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clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USB_MASK, |
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MPC837X_SICRL_USB_ULPI); |
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iounmap(immap); |
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of_node_put(np); |
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return ret; |
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} |
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#endif /* CONFIG_PPC_MPC837x */
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