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506 lines
13 KiB
506 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved. |
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* |
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* Author: John Rigby <[email protected]> |
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* |
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* Description: |
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* MPC512x Shared code |
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*/ |
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#include <linux/clk.h> |
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#include <linux/kernel.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/of_platform.h> |
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#include <linux/fsl-diu-fb.h> |
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#include <linux/memblock.h> |
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#include <sysdev/fsl_soc.h> |
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#include <asm/cacheflush.h> |
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#include <asm/machdep.h> |
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#include <asm/ipic.h> |
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#include <asm/prom.h> |
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#include <asm/time.h> |
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#include <asm/mpc5121.h> |
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#include <asm/mpc52xx_psc.h> |
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#include "mpc512x.h" |
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static struct mpc512x_reset_module __iomem *reset_module_base; |
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static void __init mpc512x_restart_init(void) |
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{ |
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struct device_node *np; |
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const char *reset_compat; |
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reset_compat = mpc512x_select_reset_compat(); |
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np = of_find_compatible_node(NULL, NULL, reset_compat); |
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if (!np) |
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return; |
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reset_module_base = of_iomap(np, 0); |
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of_node_put(np); |
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} |
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void __noreturn mpc512x_restart(char *cmd) |
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{ |
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if (reset_module_base) { |
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/* Enable software reset "RSTE" */ |
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out_be32(&reset_module_base->rpr, 0x52535445); |
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/* Set software hard reset */ |
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out_be32(&reset_module_base->rcr, 0x2); |
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} else { |
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pr_err("Restart module not mapped.\n"); |
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} |
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for (;;) |
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; |
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} |
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struct fsl_diu_shared_fb { |
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u8 gamma[0x300]; /* 32-bit aligned! */ |
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struct diu_ad ad0; /* 32-bit aligned! */ |
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phys_addr_t fb_phys; |
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size_t fb_len; |
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bool in_use; |
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}; |
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/* receives a pixel clock spec in pico seconds, adjusts the DIU clock rate */ |
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static void mpc512x_set_pixel_clock(unsigned int pixclock) |
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{ |
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struct device_node *np; |
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struct clk *clk_diu; |
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unsigned long epsilon, minpixclock, maxpixclock; |
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unsigned long offset, want, got, delta; |
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/* lookup and enable the DIU clock */ |
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np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu"); |
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if (!np) { |
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pr_err("Could not find DIU device tree node.\n"); |
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return; |
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} |
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clk_diu = of_clk_get(np, 0); |
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if (IS_ERR(clk_diu)) { |
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/* backwards compat with device trees that lack clock specs */ |
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clk_diu = clk_get_sys(np->name, "ipg"); |
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} |
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of_node_put(np); |
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if (IS_ERR(clk_diu)) { |
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pr_err("Could not lookup DIU clock.\n"); |
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return; |
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} |
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if (clk_prepare_enable(clk_diu)) { |
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pr_err("Could not enable DIU clock.\n"); |
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return; |
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} |
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/* |
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* convert the picoseconds spec into the desired clock rate, |
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* determine the acceptable clock range for the monitor (+/- 5%), |
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* do the calculation in steps to avoid integer overflow |
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*/ |
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pr_debug("DIU pixclock in ps - %u\n", pixclock); |
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pixclock = (1000000000 / pixclock) * 1000; |
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pr_debug("DIU pixclock freq - %u\n", pixclock); |
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epsilon = pixclock / 20; /* pixclock * 0.05 */ |
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pr_debug("DIU deviation - %lu\n", epsilon); |
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minpixclock = pixclock - epsilon; |
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maxpixclock = pixclock + epsilon; |
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pr_debug("DIU minpixclock - %lu\n", minpixclock); |
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pr_debug("DIU maxpixclock - %lu\n", maxpixclock); |
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/* |
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* check whether the DIU supports the desired pixel clock |
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* |
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* - simply request the desired clock and see what the |
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* platform's clock driver will make of it, assuming that it |
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* will setup the best approximation of the requested value |
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* - try other candidate frequencies in the order of decreasing |
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* preference (i.e. with increasing distance from the desired |
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* pixel clock, and checking the lower frequency before the |
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* higher frequency to not overload the hardware) until the |
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* first match is found -- any potential subsequent match |
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* would only be as good as the former match or typically |
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* would be less preferrable |
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* |
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* the offset increment of pixelclock divided by 64 is an |
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* arbitrary choice -- it's simple to calculate, in the typical |
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* case we expect the first check to succeed already, in the |
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* worst case seven frequencies get tested (the exact center and |
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* three more values each to the left and to the right) before |
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* the 5% tolerance window is exceeded, resulting in fast enough |
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* execution yet high enough probability of finding a suitable |
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* value, while the error rate will be in the order of single |
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* percents |
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*/ |
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for (offset = 0; offset <= epsilon; offset += pixclock / 64) { |
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want = pixclock - offset; |
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pr_debug("DIU checking clock - %lu\n", want); |
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clk_set_rate(clk_diu, want); |
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got = clk_get_rate(clk_diu); |
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delta = abs(pixclock - got); |
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if (delta < epsilon) |
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break; |
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if (!offset) |
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continue; |
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want = pixclock + offset; |
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pr_debug("DIU checking clock - %lu\n", want); |
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clk_set_rate(clk_diu, want); |
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got = clk_get_rate(clk_diu); |
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delta = abs(pixclock - got); |
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if (delta < epsilon) |
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break; |
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} |
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if (offset <= epsilon) { |
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pr_debug("DIU clock accepted - %lu\n", want); |
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pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n", |
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pixclock, got, delta, epsilon); |
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return; |
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} |
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pr_warn("DIU pixclock auto search unsuccessful\n"); |
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/* |
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* what is the most appropriate action to take when the search |
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* for an available pixel clock which is acceptable to the |
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* monitor has failed? disable the DIU (clock) or just provide |
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* a "best effort"? we go with the latter |
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*/ |
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pr_warn("DIU pixclock best effort fallback (backend's choice)\n"); |
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clk_set_rate(clk_diu, pixclock); |
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got = clk_get_rate(clk_diu); |
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delta = abs(pixclock - got); |
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pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n", |
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pixclock, got, delta, epsilon); |
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} |
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static enum fsl_diu_monitor_port |
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mpc512x_valid_monitor_port(enum fsl_diu_monitor_port port) |
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{ |
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return FSL_DIU_PORT_DVI; |
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} |
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static struct fsl_diu_shared_fb __attribute__ ((__aligned__(8))) diu_shared_fb; |
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static inline void mpc512x_free_bootmem(struct page *page) |
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{ |
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BUG_ON(PageTail(page)); |
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BUG_ON(page_ref_count(page) > 1); |
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free_reserved_page(page); |
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} |
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static void mpc512x_release_bootmem(void) |
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{ |
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unsigned long addr = diu_shared_fb.fb_phys & PAGE_MASK; |
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unsigned long size = diu_shared_fb.fb_len; |
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unsigned long start, end; |
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if (diu_shared_fb.in_use) { |
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start = PFN_UP(addr); |
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end = PFN_DOWN(addr + size); |
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for (; start < end; start++) |
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mpc512x_free_bootmem(pfn_to_page(start)); |
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diu_shared_fb.in_use = false; |
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} |
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diu_ops.release_bootmem = NULL; |
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} |
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/* |
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* Check if DIU was pre-initialized. If so, perform steps |
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* needed to continue displaying through the whole boot process. |
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* Move area descriptor and gamma table elsewhere, they are |
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* destroyed by bootmem allocator otherwise. The frame buffer |
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* address range will be reserved in setup_arch() after bootmem |
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* allocator is up. |
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*/ |
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static void __init mpc512x_init_diu(void) |
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{ |
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struct device_node *np; |
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struct diu __iomem *diu_reg; |
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phys_addr_t desc; |
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void __iomem *vaddr; |
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unsigned long mode, pix_fmt, res, bpp; |
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unsigned long dst; |
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np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu"); |
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if (!np) { |
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pr_err("No DIU node\n"); |
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return; |
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} |
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diu_reg = of_iomap(np, 0); |
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of_node_put(np); |
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if (!diu_reg) { |
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pr_err("Can't map DIU\n"); |
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return; |
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} |
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mode = in_be32(&diu_reg->diu_mode); |
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if (mode == MFB_MODE0) { |
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pr_info("%s: DIU OFF\n", __func__); |
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goto out; |
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} |
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desc = in_be32(&diu_reg->desc[0]); |
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vaddr = ioremap(desc, sizeof(struct diu_ad)); |
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if (!vaddr) { |
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pr_err("Can't map DIU area desc.\n"); |
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goto out; |
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} |
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memcpy(&diu_shared_fb.ad0, vaddr, sizeof(struct diu_ad)); |
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/* flush fb area descriptor */ |
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dst = (unsigned long)&diu_shared_fb.ad0; |
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flush_dcache_range(dst, dst + sizeof(struct diu_ad) - 1); |
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res = in_be32(&diu_reg->disp_size); |
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pix_fmt = in_le32(vaddr); |
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bpp = ((pix_fmt >> 16) & 0x3) + 1; |
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diu_shared_fb.fb_phys = in_le32(vaddr + 4); |
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diu_shared_fb.fb_len = ((res & 0xfff0000) >> 16) * (res & 0xfff) * bpp; |
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diu_shared_fb.in_use = true; |
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iounmap(vaddr); |
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desc = in_be32(&diu_reg->gamma); |
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vaddr = ioremap(desc, sizeof(diu_shared_fb.gamma)); |
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if (!vaddr) { |
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pr_err("Can't map DIU area desc.\n"); |
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diu_shared_fb.in_use = false; |
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goto out; |
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} |
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memcpy(&diu_shared_fb.gamma, vaddr, sizeof(diu_shared_fb.gamma)); |
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/* flush gamma table */ |
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dst = (unsigned long)&diu_shared_fb.gamma; |
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flush_dcache_range(dst, dst + sizeof(diu_shared_fb.gamma) - 1); |
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iounmap(vaddr); |
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out_be32(&diu_reg->gamma, virt_to_phys(&diu_shared_fb.gamma)); |
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out_be32(&diu_reg->desc[1], 0); |
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out_be32(&diu_reg->desc[2], 0); |
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out_be32(&diu_reg->desc[0], virt_to_phys(&diu_shared_fb.ad0)); |
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out: |
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iounmap(diu_reg); |
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} |
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static void __init mpc512x_setup_diu(void) |
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{ |
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int ret; |
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/* |
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* We do not allocate and configure new area for bitmap buffer |
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* because it would requere copying bitmap data (splash image) |
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* and so negatively affect boot time. Instead we reserve the |
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* already configured frame buffer area so that it won't be |
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* destroyed. The starting address of the area to reserve and |
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* also it's length is passed to memblock_reserve(). It will be |
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* freed later on first open of fbdev, when splash image is not |
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* needed any more. |
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*/ |
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if (diu_shared_fb.in_use) { |
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ret = memblock_reserve(diu_shared_fb.fb_phys, |
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diu_shared_fb.fb_len); |
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if (ret) { |
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pr_err("%s: reserve bootmem failed\n", __func__); |
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diu_shared_fb.in_use = false; |
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} |
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} |
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diu_ops.set_pixel_clock = mpc512x_set_pixel_clock; |
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diu_ops.valid_monitor_port = mpc512x_valid_monitor_port; |
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diu_ops.release_bootmem = mpc512x_release_bootmem; |
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} |
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void __init mpc512x_init_IRQ(void) |
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{ |
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struct device_node *np; |
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np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-ipic"); |
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if (!np) |
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return; |
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ipic_init(np, 0); |
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of_node_put(np); |
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/* |
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* Initialize the default interrupt mapping priorities, |
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* in case the boot rom changed something on us. |
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*/ |
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ipic_set_default_priority(); |
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} |
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/* |
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* Nodes to do bus probe on, soc and localbus |
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*/ |
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static const struct of_device_id of_bus_ids[] __initconst = { |
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{ .compatible = "fsl,mpc5121-immr", }, |
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{ .compatible = "fsl,mpc5121-localbus", }, |
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{ .compatible = "fsl,mpc5121-mbx", }, |
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{ .compatible = "fsl,mpc5121-nfc", }, |
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{ .compatible = "fsl,mpc5121-sram", }, |
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{ .compatible = "fsl,mpc5121-pci", }, |
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{ .compatible = "gpio-leds", }, |
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{}, |
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}; |
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static void __init mpc512x_declare_of_platform_devices(void) |
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{ |
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if (of_platform_bus_probe(NULL, of_bus_ids, NULL)) |
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printk(KERN_ERR __FILE__ ": " |
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"Error while probing of_platform bus\n"); |
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} |
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#define DEFAULT_FIFO_SIZE 16 |
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const char *mpc512x_select_psc_compat(void) |
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{ |
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if (of_machine_is_compatible("fsl,mpc5121")) |
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return "fsl,mpc5121-psc"; |
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if (of_machine_is_compatible("fsl,mpc5125")) |
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return "fsl,mpc5125-psc"; |
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return NULL; |
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} |
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const char *mpc512x_select_reset_compat(void) |
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{ |
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if (of_machine_is_compatible("fsl,mpc5121")) |
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return "fsl,mpc5121-reset"; |
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if (of_machine_is_compatible("fsl,mpc5125")) |
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return "fsl,mpc5125-reset"; |
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return NULL; |
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} |
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static unsigned int __init get_fifo_size(struct device_node *np, |
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char *prop_name) |
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{ |
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const unsigned int *fp; |
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fp = of_get_property(np, prop_name, NULL); |
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if (fp) |
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return *fp; |
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pr_warn("no %s property in %pOF node, defaulting to %d\n", |
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prop_name, np, DEFAULT_FIFO_SIZE); |
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return DEFAULT_FIFO_SIZE; |
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} |
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#define FIFOC(_base) ((struct mpc512x_psc_fifo __iomem *) \ |
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((u32)(_base) + sizeof(struct mpc52xx_psc))) |
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/* Init PSC FIFO space for TX and RX slices */ |
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static void __init mpc512x_psc_fifo_init(void) |
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{ |
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struct device_node *np; |
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void __iomem *psc; |
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unsigned int tx_fifo_size; |
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unsigned int rx_fifo_size; |
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const char *psc_compat; |
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int fifobase = 0; /* current fifo address in 32 bit words */ |
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psc_compat = mpc512x_select_psc_compat(); |
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if (!psc_compat) { |
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pr_err("%s: no compatible devices found\n", __func__); |
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return; |
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} |
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for_each_compatible_node(np, NULL, psc_compat) { |
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tx_fifo_size = get_fifo_size(np, "fsl,tx-fifo-size"); |
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rx_fifo_size = get_fifo_size(np, "fsl,rx-fifo-size"); |
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/* size in register is in 4 byte units */ |
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tx_fifo_size /= 4; |
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rx_fifo_size /= 4; |
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if (!tx_fifo_size) |
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tx_fifo_size = 1; |
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if (!rx_fifo_size) |
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rx_fifo_size = 1; |
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psc = of_iomap(np, 0); |
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if (!psc) { |
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pr_err("%s: Can't map %pOF device\n", |
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__func__, np); |
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continue; |
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} |
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/* FIFO space is 4KiB, check if requested size is available */ |
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if ((fifobase + tx_fifo_size + rx_fifo_size) > 0x1000) { |
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pr_err("%s: no fifo space available for %pOF\n", |
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__func__, np); |
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iounmap(psc); |
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/* |
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* chances are that another device requests less |
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* fifo space, so we continue. |
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*/ |
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continue; |
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} |
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/* set tx and rx fifo size registers */ |
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out_be32(&FIFOC(psc)->txsz, (fifobase << 16) | tx_fifo_size); |
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fifobase += tx_fifo_size; |
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out_be32(&FIFOC(psc)->rxsz, (fifobase << 16) | rx_fifo_size); |
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fifobase += rx_fifo_size; |
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/* reset and enable the slices */ |
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out_be32(&FIFOC(psc)->txcmd, 0x80); |
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out_be32(&FIFOC(psc)->txcmd, 0x01); |
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out_be32(&FIFOC(psc)->rxcmd, 0x80); |
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out_be32(&FIFOC(psc)->rxcmd, 0x01); |
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iounmap(psc); |
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} |
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} |
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void __init mpc512x_init_early(void) |
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{ |
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mpc512x_restart_init(); |
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if (IS_ENABLED(CONFIG_FB_FSL_DIU)) |
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mpc512x_init_diu(); |
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} |
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void __init mpc512x_init(void) |
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{ |
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mpc5121_clk_init(); |
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mpc512x_declare_of_platform_devices(); |
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mpc512x_psc_fifo_init(); |
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} |
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void __init mpc512x_setup_arch(void) |
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{ |
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if (IS_ENABLED(CONFIG_FB_FSL_DIU)) |
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mpc512x_setup_diu(); |
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} |
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/** |
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* mpc512x_cs_config - Setup chip select configuration |
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* @cs: chip select number |
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* @val: chip select configuration value |
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* |
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* Perform chip select configuration for devices on LocalPlus Bus. |
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* Intended to dynamically reconfigure the chip select parameters |
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* for configurable devices on the bus. |
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*/ |
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int mpc512x_cs_config(unsigned int cs, u32 val) |
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{ |
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static struct mpc512x_lpc __iomem *lpc; |
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struct device_node *np; |
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if (cs > 7) |
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return -EINVAL; |
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if (!lpc) { |
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np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-lpc"); |
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lpc = of_iomap(np, 0); |
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of_node_put(np); |
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if (!lpc) |
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return -ENOMEM; |
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} |
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out_be32(&lpc->cs_cfg[cs], val); |
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return 0; |
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} |
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EXPORT_SYMBOL(mpc512x_cs_config);
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