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104 lines
2.8 KiB
104 lines
2.8 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Common implementation of switch_mm_irqs_off |
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* |
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* Copyright IBM Corp. 2017 |
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*/ |
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#include <linux/mm.h> |
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#include <linux/cpu.h> |
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#include <linux/sched/mm.h> |
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#include <asm/mmu_context.h> |
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#include <asm/pgalloc.h> |
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#if defined(CONFIG_PPC32) |
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static inline void switch_mm_pgdir(struct task_struct *tsk, |
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struct mm_struct *mm) |
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{ |
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/* 32-bit keeps track of the current PGDIR in the thread struct */ |
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tsk->thread.pgdir = mm->pgd; |
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} |
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#elif defined(CONFIG_PPC_BOOK3E_64) |
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static inline void switch_mm_pgdir(struct task_struct *tsk, |
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struct mm_struct *mm) |
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{ |
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/* 64-bit Book3E keeps track of current PGD in the PACA */ |
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get_paca()->pgd = mm->pgd; |
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} |
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#else |
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static inline void switch_mm_pgdir(struct task_struct *tsk, |
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struct mm_struct *mm) { } |
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#endif |
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void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, |
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struct task_struct *tsk) |
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{ |
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bool new_on_cpu = false; |
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/* Mark this context has been used on the new CPU */ |
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if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(next))) { |
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cpumask_set_cpu(smp_processor_id(), mm_cpumask(next)); |
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inc_mm_active_cpus(next); |
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/* |
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* This full barrier orders the store to the cpumask above vs |
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* a subsequent load which allows this CPU/MMU to begin loading |
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* translations for 'next' from page table PTEs into the TLB. |
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* |
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* When using the radix MMU, that operation is the load of the |
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* MMU context id, which is then moved to SPRN_PID. |
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* |
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* For the hash MMU it is either the first load from slb_cache |
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* in switch_slb() to preload the SLBs, or the load of |
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* get_user_context which loads the context for the VSID hash |
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* to insert a new SLB, in the SLB fault handler. |
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* |
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* On the other side, the barrier is in mm/tlb-radix.c for |
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* radix which orders earlier stores to clear the PTEs before |
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* the load of mm_cpumask to check which CPU TLBs should be |
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* flushed. For hash, pte_xchg to clear the PTE includes the |
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* barrier. |
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* |
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* This full barrier is also needed by membarrier when |
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* switching between processes after store to rq->curr, before |
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* user-space memory accesses. |
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*/ |
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smp_mb(); |
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new_on_cpu = true; |
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} |
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/* Some subarchs need to track the PGD elsewhere */ |
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switch_mm_pgdir(tsk, next); |
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/* Nothing else to do if we aren't actually switching */ |
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if (prev == next) |
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return; |
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/* |
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* We must stop all altivec streams before changing the HW |
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* context |
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*/ |
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if (cpu_has_feature(CPU_FTR_ALTIVEC)) |
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asm volatile ("dssall"); |
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if (!new_on_cpu) |
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membarrier_arch_switch_mm(prev, next, tsk); |
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/* |
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* The actual HW switching method differs between the various |
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* sub architectures. Out of line for now |
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*/ |
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switch_mmu_context(prev, next, tsk); |
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} |
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#ifndef CONFIG_PPC_BOOK3S_64 |
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void arch_exit_mmap(struct mm_struct *mm) |
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{ |
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void *frag = pte_frag_get(&mm->context); |
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if (frag) |
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pte_frag_destroy(frag); |
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} |
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#endif
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