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224 lines
4.3 KiB
224 lines
4.3 KiB
/* |
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* Spreadtrum SC9836 SoC DTS file |
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* |
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* Copyright (C) 2014, Spreadtrum Communications Inc. |
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* |
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* This file is licensed under a dual GPLv2 or X11 license. |
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*/ |
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#include "sharkl64.dtsi" |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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/ { |
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compatible = "sprd,sc9836"; |
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cpus { |
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#address-cells = <2>; |
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#size-cells = <0>; |
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cpu0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x0>; |
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enable-method = "psci"; |
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}; |
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cpu1: cpu@1 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x1>; |
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enable-method = "psci"; |
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}; |
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cpu2: cpu@2 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x2>; |
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enable-method = "psci"; |
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}; |
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cpu3: cpu@3 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x3>; |
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enable-method = "psci"; |
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}; |
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}; |
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etf@10003000 { |
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compatible = "arm,coresight-tmc", "arm,primecell"; |
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reg = <0 0x10003000 0 0x1000>; |
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clocks = <&clk26mhz>; |
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clock-names = "apb_pclk"; |
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in-ports { |
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port { |
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etf_in: endpoint { |
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remote-endpoint = <&funnel_out_port0>; |
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}; |
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}; |
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}; |
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}; |
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funnel@10001000 { |
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
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reg = <0 0x10001000 0 0x1000>; |
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clocks = <&clk26mhz>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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funnel_out_port0: endpoint { |
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remote-endpoint = <&etf_in>; |
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}; |
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}; |
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}; |
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in-ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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funnel_in_port0: endpoint { |
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remote-endpoint = <&etm0_out>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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funnel_in_port1: endpoint { |
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remote-endpoint = <&etm1_out>; |
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}; |
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}; |
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port@2 { |
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reg = <2>; |
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funnel_in_port2: endpoint { |
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remote-endpoint = <&etm2_out>; |
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}; |
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}; |
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port@3 { |
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reg = <3>; |
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funnel_in_port3: endpoint { |
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remote-endpoint = <&etm3_out>; |
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}; |
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}; |
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port@4 { |
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reg = <4>; |
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funnel_in_port4: endpoint { |
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remote-endpoint = <&stm_out>; |
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}; |
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}; |
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/* Other input ports aren't connected to anyone */ |
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}; |
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}; |
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etm@10440000 { |
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compatible = "arm,coresight-etm4x", "arm,primecell"; |
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reg = <0 0x10440000 0 0x1000>; |
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cpu = <&cpu0>; |
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clocks = <&clk26mhz>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etm0_out: endpoint { |
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remote-endpoint = <&funnel_in_port0>; |
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}; |
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}; |
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}; |
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}; |
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etm@10540000 { |
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compatible = "arm,coresight-etm4x", "arm,primecell"; |
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reg = <0 0x10540000 0 0x1000>; |
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cpu = <&cpu1>; |
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clocks = <&clk26mhz>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etm1_out: endpoint { |
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remote-endpoint = <&funnel_in_port1>; |
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}; |
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}; |
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}; |
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}; |
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etm@10640000 { |
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compatible = "arm,coresight-etm4x", "arm,primecell"; |
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reg = <0 0x10640000 0 0x1000>; |
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cpu = <&cpu2>; |
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clocks = <&clk26mhz>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etm2_out: endpoint { |
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remote-endpoint = <&funnel_in_port2>; |
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}; |
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}; |
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}; |
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}; |
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etm@10740000 { |
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compatible = "arm,coresight-etm4x", "arm,primecell"; |
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reg = <0 0x10740000 0 0x1000>; |
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cpu = <&cpu3>; |
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clocks = <&clk26mhz>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etm3_out: endpoint { |
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remote-endpoint = <&funnel_in_port3>; |
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}; |
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}; |
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}; |
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}; |
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stm@10006000 { |
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compatible = "arm,coresight-stm", "arm,primecell"; |
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reg = <0 0x10006000 0 0x1000>, |
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<0 0x01000000 0 0x180000>; |
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reg-names = "stm-base", "stm-stimulus-base"; |
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clocks = <&clk26mhz>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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stm_out: endpoint { |
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remote-endpoint = <&funnel_in_port4>; |
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}; |
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}; |
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}; |
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}; |
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gic: interrupt-controller@12001000 { |
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compatible = "arm,gic-400"; |
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reg = <0 0x12001000 0 0x1000>, |
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<0 0x12002000 0 0x2000>, |
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<0 0x12004000 0 0x2000>, |
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<0 0x12006000 0 0x2000>; |
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#interrupt-cells = <3>; |
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interrupt-controller; |
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
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}; |
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psci { |
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compatible = "arm,psci"; |
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method = "smc"; |
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cpu_on = <0xc4000003>; |
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cpu_off = <0x84000002>; |
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cpu_suspend = <0xc4000001>; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
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}; |
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};
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