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2712 lines
61 KiB
2712 lines
61 KiB
// SPDX-License-Identifier: BSD-3-Clause |
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/* |
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* sc7280 SoC device tree source |
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* |
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. |
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*/ |
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#include <dt-bindings/clock/qcom,gcc-sc7280.h> |
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#include <dt-bindings/clock/qcom,rpmh.h> |
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#include <dt-bindings/interconnect/qcom,sc7280.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/mailbox/qcom-ipcc.h> |
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#include <dt-bindings/power/qcom-aoss-qmp.h> |
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#include <dt-bindings/power/qcom-rpmpd.h> |
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#include <dt-bindings/reset/qcom,sdm845-aoss.h> |
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#include <dt-bindings/reset/qcom,sdm845-pdc.h> |
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#include <dt-bindings/soc/qcom,rpmh-rsc.h> |
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#include <dt-bindings/thermal/thermal.h> |
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/ { |
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interrupt-parent = <&intc>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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chosen { }; |
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aliases { |
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mmc1 = &sdhc_1; |
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mmc2 = &sdhc_2; |
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}; |
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clocks { |
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xo_board: xo-board { |
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compatible = "fixed-clock"; |
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clock-frequency = <76800000>; |
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#clock-cells = <0>; |
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}; |
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sleep_clk: sleep-clk { |
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compatible = "fixed-clock"; |
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clock-frequency = <32000>; |
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#clock-cells = <0>; |
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}; |
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}; |
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reserved-memory { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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aop_mem: memory@80800000 { |
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reg = <0x0 0x80800000 0x0 0x60000>; |
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no-map; |
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}; |
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aop_cmd_db_mem: memory@80860000 { |
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reg = <0x0 0x80860000 0x0 0x20000>; |
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compatible = "qcom,cmd-db"; |
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no-map; |
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}; |
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smem_mem: memory@80900000 { |
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reg = <0x0 0x80900000 0x0 0x200000>; |
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no-map; |
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}; |
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cpucp_mem: memory@80b00000 { |
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no-map; |
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reg = <0x0 0x80b00000 0x0 0x100000>; |
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}; |
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ipa_fw_mem: memory@8b700000 { |
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reg = <0 0x8b700000 0 0x10000>; |
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no-map; |
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}; |
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}; |
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cpus { |
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#address-cells = <2>; |
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#size-cells = <0>; |
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CPU0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,kryo"; |
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reg = <0x0 0x0>; |
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enable-method = "psci"; |
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cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
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&LITTLE_CPU_SLEEP_1 |
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&CLUSTER_SLEEP_0>; |
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next-level-cache = <&L2_0>; |
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qcom,freq-domain = <&cpufreq_hw 0>; |
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#cooling-cells = <2>; |
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L2_0: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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L3_0: l3-cache { |
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compatible = "cache"; |
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}; |
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}; |
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}; |
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CPU1: cpu@100 { |
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device_type = "cpu"; |
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compatible = "arm,kryo"; |
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reg = <0x0 0x100>; |
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enable-method = "psci"; |
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cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
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&LITTLE_CPU_SLEEP_1 |
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&CLUSTER_SLEEP_0>; |
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next-level-cache = <&L2_100>; |
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qcom,freq-domain = <&cpufreq_hw 0>; |
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#cooling-cells = <2>; |
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L2_100: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU2: cpu@200 { |
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device_type = "cpu"; |
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compatible = "arm,kryo"; |
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reg = <0x0 0x200>; |
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enable-method = "psci"; |
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cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
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&LITTLE_CPU_SLEEP_1 |
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&CLUSTER_SLEEP_0>; |
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next-level-cache = <&L2_200>; |
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qcom,freq-domain = <&cpufreq_hw 0>; |
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#cooling-cells = <2>; |
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L2_200: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU3: cpu@300 { |
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device_type = "cpu"; |
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compatible = "arm,kryo"; |
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reg = <0x0 0x300>; |
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enable-method = "psci"; |
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cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
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&LITTLE_CPU_SLEEP_1 |
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&CLUSTER_SLEEP_0>; |
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next-level-cache = <&L2_300>; |
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qcom,freq-domain = <&cpufreq_hw 0>; |
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#cooling-cells = <2>; |
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L2_300: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU4: cpu@400 { |
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device_type = "cpu"; |
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compatible = "arm,kryo"; |
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reg = <0x0 0x400>; |
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enable-method = "psci"; |
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cpu-idle-states = <&BIG_CPU_SLEEP_0 |
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&BIG_CPU_SLEEP_1 |
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&CLUSTER_SLEEP_0>; |
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next-level-cache = <&L2_400>; |
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qcom,freq-domain = <&cpufreq_hw 1>; |
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#cooling-cells = <2>; |
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L2_400: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU5: cpu@500 { |
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device_type = "cpu"; |
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compatible = "arm,kryo"; |
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reg = <0x0 0x500>; |
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enable-method = "psci"; |
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cpu-idle-states = <&BIG_CPU_SLEEP_0 |
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&BIG_CPU_SLEEP_1 |
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&CLUSTER_SLEEP_0>; |
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next-level-cache = <&L2_500>; |
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qcom,freq-domain = <&cpufreq_hw 1>; |
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#cooling-cells = <2>; |
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L2_500: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU6: cpu@600 { |
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device_type = "cpu"; |
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compatible = "arm,kryo"; |
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reg = <0x0 0x600>; |
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enable-method = "psci"; |
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cpu-idle-states = <&BIG_CPU_SLEEP_0 |
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&BIG_CPU_SLEEP_1 |
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&CLUSTER_SLEEP_0>; |
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next-level-cache = <&L2_600>; |
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qcom,freq-domain = <&cpufreq_hw 1>; |
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#cooling-cells = <2>; |
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L2_600: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU7: cpu@700 { |
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device_type = "cpu"; |
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compatible = "arm,kryo"; |
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reg = <0x0 0x700>; |
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enable-method = "psci"; |
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cpu-idle-states = <&BIG_CPU_SLEEP_0 |
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&BIG_CPU_SLEEP_1 |
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&CLUSTER_SLEEP_0>; |
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next-level-cache = <&L2_700>; |
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qcom,freq-domain = <&cpufreq_hw 2>; |
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#cooling-cells = <2>; |
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L2_700: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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idle-states { |
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entry-method = "psci"; |
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LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { |
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compatible = "arm,idle-state"; |
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idle-state-name = "little-power-down"; |
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arm,psci-suspend-param = <0x40000003>; |
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entry-latency-us = <549>; |
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exit-latency-us = <901>; |
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min-residency-us = <1774>; |
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local-timer-stop; |
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}; |
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LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { |
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compatible = "arm,idle-state"; |
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idle-state-name = "little-rail-power-down"; |
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arm,psci-suspend-param = <0x40000004>; |
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entry-latency-us = <702>; |
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exit-latency-us = <915>; |
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min-residency-us = <4001>; |
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local-timer-stop; |
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}; |
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BIG_CPU_SLEEP_0: cpu-sleep-1-0 { |
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compatible = "arm,idle-state"; |
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idle-state-name = "big-power-down"; |
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arm,psci-suspend-param = <0x40000003>; |
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entry-latency-us = <523>; |
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exit-latency-us = <1244>; |
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min-residency-us = <2207>; |
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local-timer-stop; |
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}; |
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BIG_CPU_SLEEP_1: cpu-sleep-1-1 { |
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compatible = "arm,idle-state"; |
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idle-state-name = "big-rail-power-down"; |
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arm,psci-suspend-param = <0x40000004>; |
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entry-latency-us = <526>; |
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exit-latency-us = <1854>; |
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min-residency-us = <5555>; |
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local-timer-stop; |
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}; |
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CLUSTER_SLEEP_0: cluster-sleep-0 { |
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compatible = "arm,idle-state"; |
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idle-state-name = "cluster-power-down"; |
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arm,psci-suspend-param = <0x40003444>; |
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entry-latency-us = <3263>; |
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exit-latency-us = <6562>; |
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min-residency-us = <9926>; |
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local-timer-stop; |
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}; |
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}; |
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}; |
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memory@80000000 { |
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device_type = "memory"; |
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/* We expect the bootloader to fill in the size */ |
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reg = <0 0x80000000 0 0>; |
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}; |
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firmware { |
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scm { |
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compatible = "qcom,scm-sc7280", "qcom,scm"; |
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}; |
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}; |
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clk_virt: interconnect { |
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compatible = "qcom,sc7280-clk-virt"; |
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#interconnect-cells = <2>; |
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qcom,bcm-voters = <&apps_bcm_voter>; |
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}; |
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smem { |
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compatible = "qcom,smem"; |
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memory-region = <&smem_mem>; |
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hwlocks = <&tcsr_mutex 3>; |
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}; |
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smp2p-adsp { |
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compatible = "qcom,smp2p"; |
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qcom,smem = <443>, <429>; |
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interrupts-extended = <&ipcc IPCC_CLIENT_LPASS |
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IPCC_MPROC_SIGNAL_SMP2P |
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IRQ_TYPE_EDGE_RISING>; |
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mboxes = <&ipcc IPCC_CLIENT_LPASS |
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IPCC_MPROC_SIGNAL_SMP2P>; |
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qcom,local-pid = <0>; |
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qcom,remote-pid = <2>; |
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adsp_smp2p_out: master-kernel { |
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qcom,entry-name = "master-kernel"; |
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#qcom,smem-state-cells = <1>; |
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}; |
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adsp_smp2p_in: slave-kernel { |
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qcom,entry-name = "slave-kernel"; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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}; |
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smp2p-cdsp { |
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compatible = "qcom,smp2p"; |
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qcom,smem = <94>, <432>; |
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interrupts-extended = <&ipcc IPCC_CLIENT_CDSP |
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IPCC_MPROC_SIGNAL_SMP2P |
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IRQ_TYPE_EDGE_RISING>; |
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mboxes = <&ipcc IPCC_CLIENT_CDSP |
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IPCC_MPROC_SIGNAL_SMP2P>; |
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qcom,local-pid = <0>; |
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qcom,remote-pid = <5>; |
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cdsp_smp2p_out: master-kernel { |
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qcom,entry-name = "master-kernel"; |
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#qcom,smem-state-cells = <1>; |
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}; |
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cdsp_smp2p_in: slave-kernel { |
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qcom,entry-name = "slave-kernel"; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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}; |
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smp2p-mpss { |
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compatible = "qcom,smp2p"; |
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qcom,smem = <435>, <428>; |
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interrupts-extended = <&ipcc IPCC_CLIENT_MPSS |
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IPCC_MPROC_SIGNAL_SMP2P |
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IRQ_TYPE_EDGE_RISING>; |
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mboxes = <&ipcc IPCC_CLIENT_MPSS |
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IPCC_MPROC_SIGNAL_SMP2P>; |
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qcom,local-pid = <0>; |
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qcom,remote-pid = <1>; |
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modem_smp2p_out: master-kernel { |
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qcom,entry-name = "master-kernel"; |
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#qcom,smem-state-cells = <1>; |
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}; |
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modem_smp2p_in: slave-kernel { |
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qcom,entry-name = "slave-kernel"; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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ipa_smp2p_out: ipa-ap-to-modem { |
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qcom,entry-name = "ipa"; |
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#qcom,smem-state-cells = <1>; |
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}; |
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ipa_smp2p_in: ipa-modem-to-ap { |
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qcom,entry-name = "ipa"; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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}; |
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smp2p-wpss { |
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compatible = "qcom,smp2p"; |
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qcom,smem = <617>, <616>; |
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interrupts-extended = <&ipcc IPCC_CLIENT_WPSS |
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IPCC_MPROC_SIGNAL_SMP2P |
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IRQ_TYPE_EDGE_RISING>; |
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mboxes = <&ipcc IPCC_CLIENT_WPSS |
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IPCC_MPROC_SIGNAL_SMP2P>; |
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qcom,local-pid = <0>; |
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qcom,remote-pid = <13>; |
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wpss_smp2p_out: master-kernel { |
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qcom,entry-name = "master-kernel"; |
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#qcom,smem-state-cells = <1>; |
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}; |
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wpss_smp2p_in: slave-kernel { |
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qcom,entry-name = "slave-kernel"; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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}; |
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pmu { |
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compatible = "arm,armv8-pmuv3"; |
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; |
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}; |
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psci { |
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compatible = "arm,psci-1.0"; |
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method = "smc"; |
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}; |
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soc: soc@0 { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges = <0 0 0 0 0x10 0>; |
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dma-ranges = <0 0 0 0 0x10 0>; |
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compatible = "simple-bus"; |
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gcc: clock-controller@100000 { |
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compatible = "qcom,gcc-sc7280"; |
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reg = <0 0x00100000 0 0x1f0000>; |
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clocks = <&rpmhcc RPMH_CXO_CLK>, |
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<&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, |
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<0>, <0>, <0>, <0>, <0>, <0>; |
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clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", |
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"pcie_0_pipe_clk", "pcie_1_pipe-clk", |
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"ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", |
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"ufs_phy_tx_symbol_0_clk", |
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"usb3_phy_wrapper_gcc_usb30_pipe_clk"; |
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#clock-cells = <1>; |
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#reset-cells = <1>; |
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#power-domain-cells = <1>; |
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}; |
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ipcc: mailbox@408000 { |
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compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; |
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reg = <0 0x00408000 0 0x1000>; |
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-controller; |
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#interrupt-cells = <3>; |
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#mbox-cells = <2>; |
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}; |
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qfprom: efuse@784000 { |
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compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; |
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reg = <0 0x00784000 0 0xa20>, |
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<0 0x00780000 0 0xa20>, |
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<0 0x00782000 0 0x120>, |
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<0 0x00786000 0 0x1fff>; |
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clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; |
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clock-names = "core"; |
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power-domains = <&rpmhpd SC7280_MX>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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}; |
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sdhc_1: sdhci@7c4000 { |
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compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; |
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status = "disabled"; |
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reg = <0 0x007c4000 0 0x1000>, |
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<0 0x007c5000 0 0x1000>; |
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reg-names = "hc", "cqhci"; |
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iommus = <&apps_smmu 0xc0 0x0>; |
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interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "hc_irq", "pwr_irq"; |
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clocks = <&gcc GCC_SDCC1_APPS_CLK>, |
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<&gcc GCC_SDCC1_AHB_CLK>, |
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<&rpmhcc RPMH_CXO_CLK>; |
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clock-names = "core", "iface", "xo"; |
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interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, |
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<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; |
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interconnect-names = "sdhc-ddr","cpu-sdhc"; |
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power-domains = <&rpmhpd SC7280_CX>; |
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operating-points-v2 = <&sdhc1_opp_table>; |
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|
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bus-width = <8>; |
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supports-cqe; |
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|
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qcom,dll-config = <0x0007642c>; |
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qcom,ddr-config = <0x80040868>; |
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mmc-ddr-1_8v; |
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mmc-hs200-1_8v; |
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mmc-hs400-1_8v; |
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mmc-hs400-enhanced-strobe; |
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sdhc1_opp_table: opp-table { |
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compatible = "operating-points-v2"; |
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opp-100000000 { |
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opp-hz = /bits/ 64 <100000000>; |
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required-opps = <&rpmhpd_opp_low_svs>; |
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opp-peak-kBps = <1800000 400000>; |
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opp-avg-kBps = <100000 0>; |
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}; |
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opp-384000000 { |
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opp-hz = /bits/ 64 <384000000>; |
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required-opps = <&rpmhpd_opp_nom>; |
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opp-peak-kBps = <5400000 1600000>; |
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opp-avg-kBps = <390000 0>; |
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}; |
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}; |
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}; |
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qupv3_id_0: geniqup@9c0000 { |
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compatible = "qcom,geni-se-qup"; |
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reg = <0 0x009c0000 0 0x2000>; |
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clock-names = "m-ahb", "s-ahb"; |
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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status = "disabled"; |
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|
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uart5: serial@994000 { |
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compatible = "qcom,geni-debug-uart"; |
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reg = <0 0x00994000 0 0x4000>; |
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clock-names = "se"; |
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&qup_uart5_default>; |
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; |
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status = "disabled"; |
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}; |
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}; |
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|
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cnoc2: interconnect@1500000 { |
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reg = <0 0x01500000 0 0x1000>; |
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compatible = "qcom,sc7280-cnoc2"; |
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#interconnect-cells = <2>; |
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qcom,bcm-voters = <&apps_bcm_voter>; |
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}; |
|
|
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cnoc3: interconnect@1502000 { |
|
reg = <0 0x01502000 0 0x1000>; |
|
compatible = "qcom,sc7280-cnoc3"; |
|
#interconnect-cells = <2>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
mc_virt: interconnect@1580000 { |
|
reg = <0 0x01580000 0 0x4>; |
|
compatible = "qcom,sc7280-mc-virt"; |
|
#interconnect-cells = <2>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
system_noc: interconnect@1680000 { |
|
reg = <0 0x01680000 0 0x15480>; |
|
compatible = "qcom,sc7280-system-noc"; |
|
#interconnect-cells = <2>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
aggre1_noc: interconnect@16e0000 { |
|
compatible = "qcom,sc7280-aggre1-noc"; |
|
reg = <0 0x016e0000 0 0x1c080>; |
|
#interconnect-cells = <2>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
aggre2_noc: interconnect@1700000 { |
|
reg = <0 0x01700000 0 0x2b080>; |
|
compatible = "qcom,sc7280-aggre2-noc"; |
|
#interconnect-cells = <2>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
mmss_noc: interconnect@1740000 { |
|
reg = <0 0x01740000 0 0x1e080>; |
|
compatible = "qcom,sc7280-mmss-noc"; |
|
#interconnect-cells = <2>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
ipa: ipa@1e40000 { |
|
compatible = "qcom,sc7280-ipa"; |
|
|
|
iommus = <&apps_smmu 0x480 0x0>, |
|
<&apps_smmu 0x482 0x0>; |
|
reg = <0 0x1e40000 0 0x8000>, |
|
<0 0x1e50000 0 0x4ad0>, |
|
<0 0x1e04000 0 0x23000>; |
|
reg-names = "ipa-reg", |
|
"ipa-shared", |
|
"gsi"; |
|
|
|
interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>, |
|
<&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, |
|
<&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
|
<&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; |
|
interrupt-names = "ipa", |
|
"gsi", |
|
"ipa-clock-query", |
|
"ipa-setup-ready"; |
|
|
|
clocks = <&rpmhcc RPMH_IPA_CLK>; |
|
clock-names = "core"; |
|
|
|
interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, |
|
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; |
|
interconnect-names = "memory", |
|
"config"; |
|
|
|
qcom,smem-states = <&ipa_smp2p_out 0>, |
|
<&ipa_smp2p_out 1>; |
|
qcom,smem-state-names = "ipa-clock-enabled-valid", |
|
"ipa-clock-enabled"; |
|
|
|
status = "disabled"; |
|
}; |
|
|
|
tcsr_mutex: hwlock@1f40000 { |
|
compatible = "qcom,tcsr-mutex", "syscon"; |
|
reg = <0 0x01f40000 0 0x40000>; |
|
#hwlock-cells = <1>; |
|
}; |
|
|
|
lpasscc: lpasscc@3000000 { |
|
compatible = "qcom,sc7280-lpasscc"; |
|
reg = <0 0x03000000 0 0x40>, |
|
<0 0x03c04000 0 0x4>, |
|
<0 0x03389000 0 0x24>; |
|
reg-names = "qdsp6ss", "top_cc", "cc"; |
|
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; |
|
clock-names = "iface"; |
|
#clock-cells = <1>; |
|
}; |
|
|
|
lpass_ag_noc: interconnect@3c40000 { |
|
reg = <0 0x03c40000 0 0xf080>; |
|
compatible = "qcom,sc7280-lpass-ag-noc"; |
|
#interconnect-cells = <2>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
gpucc: clock-controller@3d90000 { |
|
compatible = "qcom,sc7280-gpucc"; |
|
reg = <0 0x03d90000 0 0x9000>; |
|
clocks = <&rpmhcc RPMH_CXO_CLK>, |
|
<&gcc GCC_GPU_GPLL0_CLK_SRC>, |
|
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; |
|
clock-names = "bi_tcxo", |
|
"gcc_gpu_gpll0_clk_src", |
|
"gcc_gpu_gpll0_div_clk_src"; |
|
#clock-cells = <1>; |
|
#reset-cells = <1>; |
|
#power-domain-cells = <1>; |
|
}; |
|
|
|
stm@6002000 { |
|
compatible = "arm,coresight-stm", "arm,primecell"; |
|
reg = <0 0x06002000 0 0x1000>, |
|
<0 0x16280000 0 0x180000>; |
|
reg-names = "stm-base", "stm-stimulus-base"; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
stm_out: endpoint { |
|
remote-endpoint = <&funnel0_in7>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
funnel@6041000 { |
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
|
reg = <0 0x06041000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
funnel0_out: endpoint { |
|
remote-endpoint = <&merge_funnel_in0>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@7 { |
|
reg = <7>; |
|
funnel0_in7: endpoint { |
|
remote-endpoint = <&stm_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
funnel@6042000 { |
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
|
reg = <0 0x06042000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
funnel1_out: endpoint { |
|
remote-endpoint = <&merge_funnel_in1>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@4 { |
|
reg = <4>; |
|
funnel1_in4: endpoint { |
|
remote-endpoint = <&apss_merge_funnel_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
funnel@6045000 { |
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
|
reg = <0 0x06045000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
merge_funnel_out: endpoint { |
|
remote-endpoint = <&swao_funnel_in>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@0 { |
|
reg = <0>; |
|
merge_funnel_in0: endpoint { |
|
remote-endpoint = <&funnel0_out>; |
|
}; |
|
}; |
|
|
|
port@1 { |
|
reg = <1>; |
|
merge_funnel_in1: endpoint { |
|
remote-endpoint = <&funnel1_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
replicator@6046000 { |
|
compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; |
|
reg = <0 0x06046000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
replicator_out: endpoint { |
|
remote-endpoint = <&etr_in>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
port { |
|
replicator_in: endpoint { |
|
remote-endpoint = <&swao_replicator_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etr@6048000 { |
|
compatible = "arm,coresight-tmc", "arm,primecell"; |
|
reg = <0 0x06048000 0 0x1000>; |
|
iommus = <&apps_smmu 0x04c0 0>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,scatter-gather; |
|
|
|
in-ports { |
|
port { |
|
etr_in: endpoint { |
|
remote-endpoint = <&replicator_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
funnel@6b04000 { |
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
|
reg = <0 0x06b04000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
swao_funnel_out: endpoint { |
|
remote-endpoint = <&etf_in>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@7 { |
|
reg = <7>; |
|
swao_funnel_in: endpoint { |
|
remote-endpoint = <&merge_funnel_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etf@6b05000 { |
|
compatible = "arm,coresight-tmc", "arm,primecell"; |
|
reg = <0 0x06b05000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
etf_out: endpoint { |
|
remote-endpoint = <&swao_replicator_in>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
port { |
|
etf_in: endpoint { |
|
remote-endpoint = <&swao_funnel_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
replicator@6b06000 { |
|
compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; |
|
reg = <0 0x06b06000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
qcom,replicator-loses-context; |
|
|
|
out-ports { |
|
port { |
|
swao_replicator_out: endpoint { |
|
remote-endpoint = <&replicator_in>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
port { |
|
swao_replicator_in: endpoint { |
|
remote-endpoint = <&etf_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7040000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07040000 0 0x1000>; |
|
|
|
cpu = <&CPU0>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
qcom,skip-power-up; |
|
|
|
out-ports { |
|
port { |
|
etm0_out: endpoint { |
|
remote-endpoint = <&apss_funnel_in0>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7140000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07140000 0 0x1000>; |
|
|
|
cpu = <&CPU1>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
qcom,skip-power-up; |
|
|
|
out-ports { |
|
port { |
|
etm1_out: endpoint { |
|
remote-endpoint = <&apss_funnel_in1>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7240000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07240000 0 0x1000>; |
|
|
|
cpu = <&CPU2>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
qcom,skip-power-up; |
|
|
|
out-ports { |
|
port { |
|
etm2_out: endpoint { |
|
remote-endpoint = <&apss_funnel_in2>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7340000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07340000 0 0x1000>; |
|
|
|
cpu = <&CPU3>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
qcom,skip-power-up; |
|
|
|
out-ports { |
|
port { |
|
etm3_out: endpoint { |
|
remote-endpoint = <&apss_funnel_in3>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7440000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07440000 0 0x1000>; |
|
|
|
cpu = <&CPU4>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
qcom,skip-power-up; |
|
|
|
out-ports { |
|
port { |
|
etm4_out: endpoint { |
|
remote-endpoint = <&apss_funnel_in4>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7540000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07540000 0 0x1000>; |
|
|
|
cpu = <&CPU5>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
qcom,skip-power-up; |
|
|
|
out-ports { |
|
port { |
|
etm5_out: endpoint { |
|
remote-endpoint = <&apss_funnel_in5>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7640000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07640000 0 0x1000>; |
|
|
|
cpu = <&CPU6>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
qcom,skip-power-up; |
|
|
|
out-ports { |
|
port { |
|
etm6_out: endpoint { |
|
remote-endpoint = <&apss_funnel_in6>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7740000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07740000 0 0x1000>; |
|
|
|
cpu = <&CPU7>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
qcom,skip-power-up; |
|
|
|
out-ports { |
|
port { |
|
etm7_out: endpoint { |
|
remote-endpoint = <&apss_funnel_in7>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
funnel@7800000 { /* APSS Funnel */ |
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
|
reg = <0 0x07800000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
apss_funnel_out: endpoint { |
|
remote-endpoint = <&apss_merge_funnel_in>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@0 { |
|
reg = <0>; |
|
apss_funnel_in0: endpoint { |
|
remote-endpoint = <&etm0_out>; |
|
}; |
|
}; |
|
|
|
port@1 { |
|
reg = <1>; |
|
apss_funnel_in1: endpoint { |
|
remote-endpoint = <&etm1_out>; |
|
}; |
|
}; |
|
|
|
port@2 { |
|
reg = <2>; |
|
apss_funnel_in2: endpoint { |
|
remote-endpoint = <&etm2_out>; |
|
}; |
|
}; |
|
|
|
port@3 { |
|
reg = <3>; |
|
apss_funnel_in3: endpoint { |
|
remote-endpoint = <&etm3_out>; |
|
}; |
|
}; |
|
|
|
port@4 { |
|
reg = <4>; |
|
apss_funnel_in4: endpoint { |
|
remote-endpoint = <&etm4_out>; |
|
}; |
|
}; |
|
|
|
port@5 { |
|
reg = <5>; |
|
apss_funnel_in5: endpoint { |
|
remote-endpoint = <&etm5_out>; |
|
}; |
|
}; |
|
|
|
port@6 { |
|
reg = <6>; |
|
apss_funnel_in6: endpoint { |
|
remote-endpoint = <&etm6_out>; |
|
}; |
|
}; |
|
|
|
port@7 { |
|
reg = <7>; |
|
apss_funnel_in7: endpoint { |
|
remote-endpoint = <&etm7_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
funnel@7810000 { |
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
|
reg = <0 0x07810000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
apss_merge_funnel_out: endpoint { |
|
remote-endpoint = <&funnel1_in4>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
port { |
|
apss_merge_funnel_in: endpoint { |
|
remote-endpoint = <&apss_funnel_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
sdhc_2: sdhci@8804000 { |
|
compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; |
|
status = "disabled"; |
|
|
|
reg = <0 0x08804000 0 0x1000>; |
|
|
|
iommus = <&apps_smmu 0x100 0x0>; |
|
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-names = "hc_irq", "pwr_irq"; |
|
|
|
clocks = <&gcc GCC_SDCC2_APPS_CLK>, |
|
<&gcc GCC_SDCC2_AHB_CLK>, |
|
<&rpmhcc RPMH_CXO_CLK>; |
|
clock-names = "core", "iface", "xo"; |
|
interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, |
|
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; |
|
interconnect-names = "sdhc-ddr","cpu-sdhc"; |
|
power-domains = <&rpmhpd SC7280_CX>; |
|
operating-points-v2 = <&sdhc2_opp_table>; |
|
|
|
bus-width = <4>; |
|
|
|
qcom,dll-config = <0x0007642c>; |
|
|
|
sdhc2_opp_table: opp-table { |
|
compatible = "operating-points-v2"; |
|
|
|
opp-100000000 { |
|
opp-hz = /bits/ 64 <100000000>; |
|
required-opps = <&rpmhpd_opp_low_svs>; |
|
opp-peak-kBps = <1800000 400000>; |
|
opp-avg-kBps = <100000 0>; |
|
}; |
|
|
|
opp-202000000 { |
|
opp-hz = /bits/ 64 <202000000>; |
|
required-opps = <&rpmhpd_opp_nom>; |
|
opp-peak-kBps = <5400000 1600000>; |
|
opp-avg-kBps = <200000 0>; |
|
}; |
|
}; |
|
|
|
}; |
|
|
|
usb_1_hsphy: phy@88e3000 { |
|
compatible = "qcom,sc7280-usb-hs-phy", |
|
"qcom,usb-snps-hs-7nm-phy"; |
|
reg = <0 0x088e3000 0 0x400>; |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>; |
|
clock-names = "ref"; |
|
|
|
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; |
|
}; |
|
|
|
usb_2_hsphy: phy@88e4000 { |
|
compatible = "qcom,sc7280-usb-hs-phy", |
|
"qcom,usb-snps-hs-7nm-phy"; |
|
reg = <0 0x088e4000 0 0x400>; |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>; |
|
clock-names = "ref"; |
|
|
|
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; |
|
}; |
|
|
|
usb_1_qmpphy: phy-wrapper@88e9000 { |
|
compatible = "qcom,sc7280-qmp-usb3-dp-phy", |
|
"qcom,sm8250-qmp-usb3-dp-phy"; |
|
reg = <0 0x088e9000 0 0x200>, |
|
<0 0x088e8000 0 0x40>, |
|
<0 0x088ea000 0 0x200>; |
|
status = "disabled"; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
|
|
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, |
|
<&rpmhcc RPMH_CXO_CLK>, |
|
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; |
|
clock-names = "aux", "ref_clk_src", "com_aux"; |
|
|
|
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, |
|
<&gcc GCC_USB3_PHY_PRIM_BCR>; |
|
reset-names = "phy", "common"; |
|
|
|
usb_1_ssphy: usb3-phy@88e9200 { |
|
reg = <0 0x088e9200 0 0x200>, |
|
<0 0x088e9400 0 0x200>, |
|
<0 0x088e9c00 0 0x400>, |
|
<0 0x088e9600 0 0x200>, |
|
<0 0x088e9800 0 0x200>, |
|
<0 0x088e9a00 0 0x100>; |
|
#clock-cells = <0>; |
|
#phy-cells = <0>; |
|
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; |
|
clock-names = "pipe0"; |
|
clock-output-names = "usb3_phy_pipe_clk_src"; |
|
}; |
|
|
|
dp_phy: dp-phy@88ea200 { |
|
reg = <0 0x088ea200 0 0x200>, |
|
<0 0x088ea400 0 0x200>, |
|
<0 0x088eac00 0 0x400>, |
|
<0 0x088ea600 0 0x200>, |
|
<0 0x088ea800 0 0x200>, |
|
<0 0x088eaa00 0 0x100>; |
|
#phy-cells = <0>; |
|
#clock-cells = <1>; |
|
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; |
|
clock-names = "pipe0"; |
|
clock-output-names = "usb3_phy_pipe_clk_src"; |
|
}; |
|
}; |
|
|
|
usb_2: usb@8cf8800 { |
|
compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; |
|
reg = <0 0x08cf8800 0 0x400>; |
|
status = "disabled"; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
dma-ranges; |
|
|
|
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, |
|
<&gcc GCC_USB30_SEC_MASTER_CLK>, |
|
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, |
|
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, |
|
<&gcc GCC_USB30_SEC_SLEEP_CLK>; |
|
clock-names = "cfg_noc", "core", "iface","mock_utmi", |
|
"sleep"; |
|
|
|
assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, |
|
<&gcc GCC_USB30_SEC_MASTER_CLK>; |
|
assigned-clock-rates = <19200000>, <200000000>; |
|
|
|
interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, |
|
<&pdc 13 IRQ_TYPE_EDGE_RISING>, |
|
<&pdc 12 IRQ_TYPE_EDGE_RISING>; |
|
interrupt-names = "hs_phy_irq", |
|
"dm_hs_phy_irq", "dp_hs_phy_irq"; |
|
|
|
power-domains = <&gcc GCC_USB30_SEC_GDSC>; |
|
|
|
resets = <&gcc GCC_USB30_SEC_BCR>; |
|
|
|
interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, |
|
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; |
|
interconnect-names = "usb-ddr", "apps-usb"; |
|
|
|
usb_2_dwc3: usb@8c00000 { |
|
compatible = "snps,dwc3"; |
|
reg = <0 0x08c00000 0 0xe000>; |
|
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; |
|
iommus = <&apps_smmu 0xa0 0x0>; |
|
snps,dis_u2_susphy_quirk; |
|
snps,dis_enblslpm_quirk; |
|
phys = <&usb_2_hsphy>; |
|
phy-names = "usb2-phy"; |
|
maximum-speed = "high-speed"; |
|
}; |
|
}; |
|
|
|
dc_noc: interconnect@90e0000 { |
|
reg = <0 0x090e0000 0 0x5080>; |
|
compatible = "qcom,sc7280-dc-noc"; |
|
#interconnect-cells = <2>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
gem_noc: interconnect@9100000 { |
|
reg = <0 0x9100000 0 0xe2200>; |
|
compatible = "qcom,sc7280-gem-noc"; |
|
#interconnect-cells = <2>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
system-cache-controller@9200000 { |
|
compatible = "qcom,sc7280-llcc"; |
|
reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; |
|
reg-names = "llcc_base", "llcc_broadcast_base"; |
|
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
nsp_noc: interconnect@a0c0000 { |
|
reg = <0 0x0a0c0000 0 0x10000>; |
|
compatible = "qcom,sc7280-nsp-noc"; |
|
#interconnect-cells = <2>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
usb_1: usb@a6f8800 { |
|
compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; |
|
reg = <0 0x0a6f8800 0 0x400>; |
|
status = "disabled"; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
dma-ranges; |
|
|
|
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, |
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>, |
|
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, |
|
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, |
|
<&gcc GCC_USB30_PRIM_SLEEP_CLK>; |
|
clock-names = "cfg_noc", "core", "iface", "mock_utmi", |
|
"sleep"; |
|
|
|
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, |
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>; |
|
assigned-clock-rates = <19200000>, <200000000>; |
|
|
|
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
|
<&pdc 14 IRQ_TYPE_EDGE_BOTH>, |
|
<&pdc 15 IRQ_TYPE_EDGE_BOTH>, |
|
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", |
|
"dm_hs_phy_irq", "ss_phy_irq"; |
|
|
|
power-domains = <&gcc GCC_USB30_PRIM_GDSC>; |
|
|
|
resets = <&gcc GCC_USB30_PRIM_BCR>; |
|
|
|
interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, |
|
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; |
|
interconnect-names = "usb-ddr", "apps-usb"; |
|
|
|
usb_1_dwc3: usb@a600000 { |
|
compatible = "snps,dwc3"; |
|
reg = <0 0x0a600000 0 0xe000>; |
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
|
iommus = <&apps_smmu 0xe0 0x0>; |
|
snps,dis_u2_susphy_quirk; |
|
snps,dis_enblslpm_quirk; |
|
phys = <&usb_1_hsphy>, <&usb_1_ssphy>; |
|
phy-names = "usb2-phy", "usb3-phy"; |
|
maximum-speed = "super-speed"; |
|
}; |
|
}; |
|
|
|
videocc: clock-controller@aaf0000 { |
|
compatible = "qcom,sc7280-videocc"; |
|
reg = <0 0xaaf0000 0 0x10000>; |
|
clocks = <&rpmhcc RPMH_CXO_CLK>, |
|
<&rpmhcc RPMH_CXO_CLK_A>; |
|
clock-names = "bi_tcxo", "bi_tcxo_ao"; |
|
#clock-cells = <1>; |
|
#reset-cells = <1>; |
|
#power-domain-cells = <1>; |
|
}; |
|
|
|
dispcc: clock-controller@af00000 { |
|
compatible = "qcom,sc7280-dispcc"; |
|
reg = <0 0xaf00000 0 0x20000>; |
|
clocks = <&rpmhcc RPMH_CXO_CLK>, |
|
<&gcc GCC_DISP_GPLL0_CLK_SRC>, |
|
<0>, <0>, <0>, <0>, <0>, <0>; |
|
clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", |
|
"dsi0_phy_pll_out_byteclk", |
|
"dsi0_phy_pll_out_dsiclk", |
|
"dp_phy_pll_link_clk", |
|
"dp_phy_pll_vco_div_clk", |
|
"edp_phy_pll_link_clk", |
|
"edp_phy_pll_vco_div_clk"; |
|
#clock-cells = <1>; |
|
#reset-cells = <1>; |
|
#power-domain-cells = <1>; |
|
}; |
|
|
|
pdc: interrupt-controller@b220000 { |
|
compatible = "qcom,sc7280-pdc", "qcom,pdc"; |
|
reg = <0 0x0b220000 0 0x30000>; |
|
qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, |
|
<55 306 4>, <59 312 3>, <62 374 2>, |
|
<64 434 2>, <66 438 3>, <69 86 1>, |
|
<70 520 54>, <124 609 31>, <155 63 1>, |
|
<156 716 12>; |
|
#interrupt-cells = <2>; |
|
interrupt-parent = <&intc>; |
|
interrupt-controller; |
|
}; |
|
|
|
pdc_reset: reset-controller@b5e0000 { |
|
compatible = "qcom,sc7280-pdc-global"; |
|
reg = <0 0x0b5e0000 0 0x20000>; |
|
#reset-cells = <1>; |
|
}; |
|
|
|
tsens0: thermal-sensor@c263000 { |
|
compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; |
|
reg = <0 0x0c263000 0 0x1ff>, /* TM */ |
|
<0 0x0c222000 0 0x1ff>; /* SROT */ |
|
#qcom,sensors = <15>; |
|
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-names = "uplow","critical"; |
|
#thermal-sensor-cells = <1>; |
|
}; |
|
|
|
tsens1: thermal-sensor@c265000 { |
|
compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; |
|
reg = <0 0x0c265000 0 0x1ff>, /* TM */ |
|
<0 0x0c223000 0 0x1ff>; /* SROT */ |
|
#qcom,sensors = <12>; |
|
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-names = "uplow","critical"; |
|
#thermal-sensor-cells = <1>; |
|
}; |
|
|
|
aoss_reset: reset-controller@c2a0000 { |
|
compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; |
|
reg = <0 0x0c2a0000 0 0x31000>; |
|
#reset-cells = <1>; |
|
}; |
|
|
|
aoss_qmp: power-controller@c300000 { |
|
compatible = "qcom,sc7280-aoss-qmp"; |
|
reg = <0 0x0c300000 0 0x100000>; |
|
interrupts-extended = <&ipcc IPCC_CLIENT_AOP |
|
IPCC_MPROC_SIGNAL_GLINK_QMP |
|
IRQ_TYPE_EDGE_RISING>; |
|
mboxes = <&ipcc IPCC_CLIENT_AOP |
|
IPCC_MPROC_SIGNAL_GLINK_QMP>; |
|
|
|
#clock-cells = <0>; |
|
#power-domain-cells = <1>; |
|
}; |
|
|
|
spmi_bus: spmi@c440000 { |
|
compatible = "qcom,spmi-pmic-arb"; |
|
reg = <0 0x0c440000 0 0x1100>, |
|
<0 0x0c600000 0 0x2000000>, |
|
<0 0x0e600000 0 0x100000>, |
|
<0 0x0e700000 0 0xa0000>, |
|
<0 0x0c40a000 0 0x26000>; |
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
|
interrupt-names = "periph_irq"; |
|
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; |
|
qcom,ee = <0>; |
|
qcom,channel = <0>; |
|
#address-cells = <1>; |
|
#size-cells = <1>; |
|
interrupt-controller; |
|
#interrupt-cells = <4>; |
|
}; |
|
|
|
tlmm: pinctrl@f100000 { |
|
compatible = "qcom,sc7280-pinctrl"; |
|
reg = <0 0x0f100000 0 0x300000>; |
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
|
gpio-controller; |
|
#gpio-cells = <2>; |
|
interrupt-controller; |
|
#interrupt-cells = <2>; |
|
gpio-ranges = <&tlmm 0 0 175>; |
|
wakeup-parent = <&pdc>; |
|
|
|
qup_uart5_default: qup-uart5-default { |
|
pins = "gpio46", "gpio47"; |
|
function = "qup13"; |
|
}; |
|
|
|
sdc1_on: sdc1-on { |
|
clk { |
|
pins = "sdc1_clk"; |
|
}; |
|
|
|
cmd { |
|
pins = "sdc1_cmd"; |
|
}; |
|
|
|
data { |
|
pins = "sdc1_data"; |
|
}; |
|
|
|
rclk { |
|
pins = "sdc1_rclk"; |
|
}; |
|
}; |
|
|
|
sdc1_off: sdc1-off { |
|
clk { |
|
pins = "sdc1_clk"; |
|
drive-strength = <2>; |
|
bias-bus-hold; |
|
}; |
|
|
|
cmd { |
|
pins = "sdc1_cmd"; |
|
drive-strength = <2>; |
|
bias-bus-hold; |
|
}; |
|
|
|
data { |
|
pins = "sdc1_data"; |
|
drive-strength = <2>; |
|
bias-bus-hold; |
|
}; |
|
|
|
rclk { |
|
pins = "sdc1_rclk"; |
|
bias-bus-hold; |
|
}; |
|
}; |
|
|
|
sdc2_on: sdc2-on { |
|
clk { |
|
pins = "sdc2_clk"; |
|
}; |
|
|
|
cmd { |
|
pins = "sdc2_cmd"; |
|
}; |
|
|
|
data { |
|
pins = "sdc2_data"; |
|
}; |
|
|
|
sd-cd { |
|
pins = "gpio91"; |
|
}; |
|
}; |
|
|
|
sdc2_off: sdc2-off { |
|
clk { |
|
pins = "sdc2_clk"; |
|
drive-strength = <2>; |
|
bias-bus-hold; |
|
}; |
|
|
|
cmd { |
|
pins ="sdc2_cmd"; |
|
drive-strength = <2>; |
|
bias-bus-hold; |
|
}; |
|
|
|
data { |
|
pins ="sdc2_data"; |
|
drive-strength = <2>; |
|
bias-bus-hold; |
|
}; |
|
}; |
|
}; |
|
|
|
apps_smmu: iommu@15000000 { |
|
compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; |
|
reg = <0 0x15000000 0 0x100000>; |
|
#iommu-cells = <2>; |
|
#global-interrupts = <1>; |
|
dma-coherent; |
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
intc: interrupt-controller@17a00000 { |
|
compatible = "arm,gic-v3"; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
#interrupt-cells = <3>; |
|
interrupt-controller; |
|
reg = <0 0x17a00000 0 0x10000>, /* GICD */ |
|
<0 0x17a60000 0 0x100000>; /* GICR * 8 */ |
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; |
|
|
|
gic-its@17a40000 { |
|
compatible = "arm,gic-v3-its"; |
|
msi-controller; |
|
#msi-cells = <1>; |
|
reg = <0 0x17a40000 0 0x20000>; |
|
status = "disabled"; |
|
}; |
|
}; |
|
|
|
watchdog@17c10000 { |
|
compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; |
|
reg = <0 0x17c10000 0 0x1000>; |
|
clocks = <&sleep_clk>; |
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
timer@17c20000 { |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
compatible = "arm,armv7-timer-mem"; |
|
reg = <0 0x17c20000 0 0x1000>; |
|
|
|
frame@17c21000 { |
|
frame-number = <0>; |
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0 0x17c21000 0 0x1000>, |
|
<0 0x17c22000 0 0x1000>; |
|
}; |
|
|
|
frame@17c23000 { |
|
frame-number = <1>; |
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0 0x17c23000 0 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@17c25000 { |
|
frame-number = <2>; |
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0 0x17c25000 0 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@17c27000 { |
|
frame-number = <3>; |
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0 0x17c27000 0 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@17c29000 { |
|
frame-number = <4>; |
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0 0x17c29000 0 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@17c2b000 { |
|
frame-number = <5>; |
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0 0x17c2b000 0 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@17c2d000 { |
|
frame-number = <6>; |
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0 0x17c2d000 0 0x1000>; |
|
status = "disabled"; |
|
}; |
|
}; |
|
|
|
apps_rsc: rsc@18200000 { |
|
compatible = "qcom,rpmh-rsc"; |
|
reg = <0 0x18200000 0 0x10000>, |
|
<0 0x18210000 0 0x10000>, |
|
<0 0x18220000 0 0x10000>; |
|
reg-names = "drv-0", "drv-1", "drv-2"; |
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
|
qcom,tcs-offset = <0xd00>; |
|
qcom,drv-id = <2>; |
|
qcom,tcs-config = <ACTIVE_TCS 2>, |
|
<SLEEP_TCS 3>, |
|
<WAKE_TCS 3>, |
|
<CONTROL_TCS 1>; |
|
|
|
apps_bcm_voter: bcm-voter { |
|
compatible = "qcom,bcm-voter"; |
|
}; |
|
|
|
rpmhpd: power-controller { |
|
compatible = "qcom,sc7280-rpmhpd"; |
|
#power-domain-cells = <1>; |
|
operating-points-v2 = <&rpmhpd_opp_table>; |
|
|
|
rpmhpd_opp_table: opp-table { |
|
compatible = "operating-points-v2"; |
|
|
|
rpmhpd_opp_ret: opp1 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; |
|
}; |
|
|
|
rpmhpd_opp_low_svs: opp2 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; |
|
}; |
|
|
|
rpmhpd_opp_svs: opp3 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS>; |
|
}; |
|
|
|
rpmhpd_opp_svs_l1: opp4 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
|
}; |
|
|
|
rpmhpd_opp_svs_l2: opp5 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; |
|
}; |
|
|
|
rpmhpd_opp_nom: opp6 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM>; |
|
}; |
|
|
|
rpmhpd_opp_nom_l1: opp7 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; |
|
}; |
|
|
|
rpmhpd_opp_turbo: opp8 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; |
|
}; |
|
|
|
rpmhpd_opp_turbo_l1: opp9 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; |
|
}; |
|
}; |
|
}; |
|
|
|
rpmhcc: clock-controller { |
|
compatible = "qcom,sc7280-rpmh-clk"; |
|
clocks = <&xo_board>; |
|
clock-names = "xo"; |
|
#clock-cells = <1>; |
|
}; |
|
}; |
|
|
|
cpufreq_hw: cpufreq@18591000 { |
|
compatible = "qcom,cpufreq-epss"; |
|
reg = <0 0x18591000 0 0x1000>, |
|
<0 0x18592000 0 0x1000>, |
|
<0 0x18593000 0 0x1000>; |
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; |
|
clock-names = "xo", "alternate"; |
|
#freq-domain-cells = <1>; |
|
}; |
|
}; |
|
|
|
thermal_zones: thermal-zones { |
|
cpu0-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens0 1>; |
|
|
|
trips { |
|
cpu0_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu0_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu0_crit: cpu-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu0_alert0>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu0_alert1>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu1-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens0 2>; |
|
|
|
trips { |
|
cpu1_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu1_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu1_crit: cpu-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu1_alert0>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu1_alert1>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu2-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens0 3>; |
|
|
|
trips { |
|
cpu2_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu2_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu2_crit: cpu-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu2_alert0>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu2_alert1>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu3-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens0 4>; |
|
|
|
trips { |
|
cpu3_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu3_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu3_crit: cpu-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu3_alert0>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu3_alert1>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu4-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens0 7>; |
|
|
|
trips { |
|
cpu4_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu4_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu4_crit: cpu-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu4_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu4_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu5-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens0 8>; |
|
|
|
trips { |
|
cpu5_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu5_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu5_crit: cpu-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu5_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu5_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu6-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens0 9>; |
|
|
|
trips { |
|
cpu6_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu6_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu6_crit: cpu-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu6_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu6_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu7-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens0 10>; |
|
|
|
trips { |
|
cpu7_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu7_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu7_crit: cpu-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu7_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu7_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu8-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens0 11>; |
|
|
|
trips { |
|
cpu8_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu8_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu8_crit: cpu-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu8_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu8_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu9-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens0 12>; |
|
|
|
trips { |
|
cpu9_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu9_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu9_crit: cpu-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu9_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu9_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu10-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens0 13>; |
|
|
|
trips { |
|
cpu10_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu10_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu10_crit: cpu-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu10_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu10_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu11-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens0 14>; |
|
|
|
trips { |
|
cpu11_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu11_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu11_crit: cpu-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu11_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu11_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
aoss0-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens0 0>; |
|
|
|
trips { |
|
aoss0_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
|
|
aoss0_crit: aoss0-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
|
|
aoss1-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens1 0>; |
|
|
|
trips { |
|
aoss1_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
|
|
aoss1_crit: aoss1-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
|
|
cpuss0-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens0 5>; |
|
|
|
trips { |
|
cpuss0_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
cpuss0_crit: cluster0-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
|
|
cpuss1-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens0 6>; |
|
|
|
trips { |
|
cpuss1_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
cpuss1_crit: cluster0-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
|
|
gpuss0-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens1 1>; |
|
|
|
trips { |
|
gpuss0_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
|
|
gpuss0_crit: gpuss0-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
|
|
gpuss1-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens1 2>; |
|
|
|
trips { |
|
gpuss1_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
|
|
gpuss1_crit: gpuss1-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
|
|
nspss0-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens1 3>; |
|
|
|
trips { |
|
nspss0_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
|
|
nspss0_crit: nspss0-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
|
|
nspss1-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens1 4>; |
|
|
|
trips { |
|
nspss1_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
|
|
nspss1_crit: nspss1-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
|
|
video-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens1 5>; |
|
|
|
trips { |
|
video_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
|
|
video_crit: video-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
|
|
ddr-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens1 6>; |
|
|
|
trips { |
|
ddr_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
|
|
ddr_crit: ddr-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
|
|
mdmss0-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens1 7>; |
|
|
|
trips { |
|
mdmss0_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
|
|
mdmss0_crit: mdmss0-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
|
|
mdmss1-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens1 8>; |
|
|
|
trips { |
|
mdmss1_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
|
|
mdmss1_crit: mdmss1-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
|
|
mdmss2-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens1 9>; |
|
|
|
trips { |
|
mdmss2_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
|
|
mdmss2_crit: mdmss2-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
|
|
mdmss3-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens1 10>; |
|
|
|
trips { |
|
mdmss3_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
|
|
mdmss3_crit: mdmss3-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
|
|
camera0-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <0>; |
|
|
|
thermal-sensors = <&tsens1 11>; |
|
|
|
trips { |
|
camera0_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
|
|
camera0_crit: camera0-crit { |
|
temperature = <110000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
timer { |
|
compatible = "arm,armv8-timer"; |
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
|
}; |
|
};
|
|
|