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352 lines
8.5 KiB
352 lines
8.5 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* dts file for lg1313 SoC |
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* |
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* Copyright (C) 2016, LG Electronics |
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*/ |
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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/ { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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compatible = "lge,lg1313"; |
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interrupt-parent = <&gic>; |
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cpus { |
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#address-cells = <2>; |
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#size-cells = <0>; |
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cpu0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x0>; |
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next-level-cache = <&L2_0>; |
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}; |
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cpu1: cpu@1 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x1>; |
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enable-method = "psci"; |
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next-level-cache = <&L2_0>; |
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}; |
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cpu2: cpu@2 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x2>; |
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enable-method = "psci"; |
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next-level-cache = <&L2_0>; |
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}; |
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cpu3: cpu@3 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x3>; |
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enable-method = "psci"; |
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next-level-cache = <&L2_0>; |
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}; |
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L2_0: l2-cache0 { |
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compatible = "cache"; |
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}; |
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}; |
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psci { |
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compatible = "arm,psci-0.2", "arm,psci"; |
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method = "smc"; |
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cpu_suspend = <0x84000001>; |
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cpu_off = <0x84000002>; |
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cpu_on = <0x84000003>; |
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}; |
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gic: interrupt-controller@c0001000 { |
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#interrupt-cells = <3>; |
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compatible = "arm,gic-400"; |
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interrupt-controller; |
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reg = <0x0 0xc0001000 0x1000>, |
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<0x0 0xc0002000 0x2000>, |
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<0x0 0xc0004000 0x2000>, |
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<0x0 0xc0006000 0x2000>; |
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}; |
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pmu { |
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compatible = "arm,cortex-a53-pmu"; |
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interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-affinity = <&cpu0>, |
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<&cpu1>, |
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<&cpu2>, |
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<&cpu3>; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) | |
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IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) | |
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IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) | |
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IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) | |
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IRQ_TYPE_LEVEL_LOW)>; |
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}; |
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clk_bus: clk_bus { |
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#clock-cells = <0>; |
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compatible = "fixed-clock"; |
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clock-frequency = <198000000>; |
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clock-output-names = "BUSCLK"; |
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}; |
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soc { |
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#address-cells = <2>; |
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#size-cells = <1>; |
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compatible = "simple-bus"; |
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interrupt-parent = <&gic>; |
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ranges; |
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eth0: ethernet@c3700000 { |
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compatible = "cdns,gem"; |
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reg = <0x0 0xc3700000 0x1000>; |
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clk_bus>, <&clk_bus>; |
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clock-names = "hclk", "pclk"; |
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phy-mode = "rmii"; |
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/* Filled in by boot */ |
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mac-address = [ 00 00 00 00 00 00 ]; |
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}; |
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}; |
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amba { |
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#address-cells = <2>; |
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#size-cells = <1>; |
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#interrupt-cells = <3>; |
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compatible = "simple-bus"; |
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interrupt-parent = <&gic>; |
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ranges; |
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timers: timer@fd100000 { |
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compatible = "arm,sp804", "arm,primecell"; |
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reg = <0x0 0xfd100000 0x1000>; |
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>; |
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clock-names = "timer0clk", "timer1clk", "apb_pclk"; |
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}; |
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wdog: watchdog@fd200000 { |
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compatible = "arm,sp805", "arm,primecell"; |
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reg = <0x0 0xfd200000 0x1000>; |
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clk_bus>, <&clk_bus>; |
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clock-names = "wdog_clk", "apb_pclk"; |
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}; |
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uart0: serial@fe000000 { |
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compatible = "arm,pl011", "arm,primecell"; |
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reg = <0x0 0xfe000000 0x1000>; |
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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status="disabled"; |
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}; |
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uart1: serial@fe100000 { |
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compatible = "arm,pl011", "arm,primecell"; |
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reg = <0x0 0xfe100000 0x1000>; |
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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status="disabled"; |
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}; |
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uart2: serial@fe200000 { |
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compatible = "arm,pl011", "arm,primecell"; |
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reg = <0x0 0xfe200000 0x1000>; |
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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status="disabled"; |
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}; |
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spi0: spi@fe800000 { |
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compatible = "arm,pl022", "arm,primecell"; |
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reg = <0x0 0xfe800000 0x1000>; |
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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}; |
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spi1: spi@fe900000 { |
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compatible = "arm,pl022", "arm,primecell"; |
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reg = <0x0 0xfe900000 0x1000>; |
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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}; |
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dmac0: dma@c1128000 { |
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compatible = "arm,pl330", "arm,primecell"; |
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reg = <0x0 0xc1128000 0x1000>; |
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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}; |
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gpio0: gpio@fd400000 { |
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#gpio-cells = <2>; |
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compatible = "arm,pl061", "arm,primecell"; |
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gpio-controller; |
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reg = <0x0 0xfd400000 0x1000>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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status="disabled"; |
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}; |
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gpio1: gpio@fd410000 { |
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#gpio-cells = <2>; |
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compatible = "arm,pl061", "arm,primecell"; |
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gpio-controller; |
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reg = <0x0 0xfd410000 0x1000>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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status="disabled"; |
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}; |
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gpio2: gpio@fd420000 { |
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#gpio-cells = <2>; |
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compatible = "arm,pl061", "arm,primecell"; |
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gpio-controller; |
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reg = <0x0 0xfd420000 0x1000>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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status="disabled"; |
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}; |
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gpio3: gpio@fd430000 { |
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#gpio-cells = <2>; |
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compatible = "arm,pl061", "arm,primecell"; |
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gpio-controller; |
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reg = <0x0 0xfd430000 0x1000>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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}; |
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gpio4: gpio@fd440000 { |
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#gpio-cells = <2>; |
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compatible = "arm,pl061", "arm,primecell"; |
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gpio-controller; |
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reg = <0x0 0xfd440000 0x1000>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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status="disabled"; |
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}; |
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gpio5: gpio@fd450000 { |
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#gpio-cells = <2>; |
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compatible = "arm,pl061", "arm,primecell"; |
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gpio-controller; |
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reg = <0x0 0xfd450000 0x1000>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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status="disabled"; |
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}; |
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gpio6: gpio@fd460000 { |
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#gpio-cells = <2>; |
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compatible = "arm,pl061", "arm,primecell"; |
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gpio-controller; |
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reg = <0x0 0xfd460000 0x1000>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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status="disabled"; |
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}; |
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gpio7: gpio@fd470000 { |
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#gpio-cells = <2>; |
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compatible = "arm,pl061", "arm,primecell"; |
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gpio-controller; |
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reg = <0x0 0xfd470000 0x1000>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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status="disabled"; |
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}; |
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gpio8: gpio@fd480000 { |
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#gpio-cells = <2>; |
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compatible = "arm,pl061", "arm,primecell"; |
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gpio-controller; |
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reg = <0x0 0xfd480000 0x1000>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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status="disabled"; |
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}; |
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gpio9: gpio@fd490000 { |
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#gpio-cells = <2>; |
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compatible = "arm,pl061", "arm,primecell"; |
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gpio-controller; |
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reg = <0x0 0xfd490000 0x1000>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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status="disabled"; |
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}; |
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gpio10: gpio@fd4a0000 { |
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#gpio-cells = <2>; |
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compatible = "arm,pl061", "arm,primecell"; |
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gpio-controller; |
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reg = <0x0 0xfd4a0000 0x1000>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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status="disabled"; |
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}; |
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gpio11: gpio@fd4b0000 { |
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#gpio-cells = <2>; |
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compatible = "arm,pl061", "arm,primecell"; |
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gpio-controller; |
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reg = <0x0 0xfd4b0000 0x1000>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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}; |
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gpio12: gpio@fd4c0000 { |
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#gpio-cells = <2>; |
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compatible = "arm,pl061", "arm,primecell"; |
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gpio-controller; |
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reg = <0x0 0xfd4c0000 0x1000>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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status="disabled"; |
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}; |
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gpio13: gpio@fd4d0000 { |
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#gpio-cells = <2>; |
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compatible = "arm,pl061", "arm,primecell"; |
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gpio-controller; |
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reg = <0x0 0xfd4d0000 0x1000>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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status="disabled"; |
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}; |
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gpio14: gpio@fd4e0000 { |
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#gpio-cells = <2>; |
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compatible = "arm,pl061", "arm,primecell"; |
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gpio-controller; |
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reg = <0x0 0xfd4e0000 0x1000>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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status="disabled"; |
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}; |
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gpio15: gpio@fd4f0000 { |
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#gpio-cells = <2>; |
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compatible = "arm,pl061", "arm,primecell"; |
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gpio-controller; |
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reg = <0x0 0xfd4f0000 0x1000>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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status="disabled"; |
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}; |
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gpio16: gpio@fd500000 { |
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#gpio-cells = <2>; |
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compatible = "arm,pl061", "arm,primecell"; |
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gpio-controller; |
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reg = <0x0 0xfd500000 0x1000>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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status="disabled"; |
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}; |
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gpio17: gpio@fd510000 { |
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#gpio-cells = <2>; |
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compatible = "arm,pl061", "arm,primecell"; |
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gpio-controller; |
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reg = <0x0 0xfd510000 0x1000>; |
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clocks = <&clk_bus>; |
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clock-names = "apb_pclk"; |
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}; |
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}; |
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};
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