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365 lines
7.4 KiB
365 lines
7.4 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/** |
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* dts file for Hisilicon D02 Development Board |
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* |
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* Copyright (C) 2014,2015 HiSilicon Ltd. |
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*/ |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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/ { |
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compatible = "hisilicon,hip05-d02"; |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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psci { |
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compatible = "arm,psci-0.2"; |
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method = "smc"; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu-map { |
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cluster0 { |
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core0 { |
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cpu = <&cpu0>; |
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}; |
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core1 { |
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cpu = <&cpu1>; |
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}; |
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core2 { |
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cpu = <&cpu2>; |
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}; |
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core3 { |
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cpu = <&cpu3>; |
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}; |
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}; |
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cluster1 { |
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core0 { |
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cpu = <&cpu4>; |
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}; |
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core1 { |
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cpu = <&cpu5>; |
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}; |
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core2 { |
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cpu = <&cpu6>; |
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}; |
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core3 { |
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cpu = <&cpu7>; |
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}; |
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}; |
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cluster2 { |
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core0 { |
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cpu = <&cpu8>; |
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}; |
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core1 { |
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cpu = <&cpu9>; |
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}; |
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core2 { |
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cpu = <&cpu10>; |
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}; |
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core3 { |
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cpu = <&cpu11>; |
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}; |
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}; |
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cluster3 { |
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core0 { |
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cpu = <&cpu12>; |
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}; |
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core1 { |
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cpu = <&cpu13>; |
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}; |
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core2 { |
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cpu = <&cpu14>; |
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}; |
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core3 { |
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cpu = <&cpu15>; |
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}; |
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}; |
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}; |
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cpu0: cpu@20000 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x20000>; |
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enable-method = "psci"; |
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next-level-cache = <&cluster0_l2>; |
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}; |
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cpu1: cpu@20001 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x20001>; |
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enable-method = "psci"; |
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next-level-cache = <&cluster0_l2>; |
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}; |
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cpu2: cpu@20002 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x20002>; |
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enable-method = "psci"; |
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next-level-cache = <&cluster0_l2>; |
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}; |
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cpu3: cpu@20003 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x20003>; |
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enable-method = "psci"; |
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next-level-cache = <&cluster0_l2>; |
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}; |
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cpu4: cpu@20100 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x20100>; |
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enable-method = "psci"; |
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next-level-cache = <&cluster1_l2>; |
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}; |
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cpu5: cpu@20101 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x20101>; |
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enable-method = "psci"; |
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next-level-cache = <&cluster1_l2>; |
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}; |
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cpu6: cpu@20102 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x20102>; |
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enable-method = "psci"; |
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next-level-cache = <&cluster1_l2>; |
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}; |
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cpu7: cpu@20103 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x20103>; |
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enable-method = "psci"; |
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next-level-cache = <&cluster1_l2>; |
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}; |
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cpu8: cpu@20200 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x20200>; |
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enable-method = "psci"; |
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next-level-cache = <&cluster2_l2>; |
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}; |
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cpu9: cpu@20201 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x20201>; |
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enable-method = "psci"; |
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next-level-cache = <&cluster2_l2>; |
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}; |
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cpu10: cpu@20202 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x20202>; |
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enable-method = "psci"; |
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next-level-cache = <&cluster2_l2>; |
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}; |
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cpu11: cpu@20203 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x20203>; |
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enable-method = "psci"; |
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next-level-cache = <&cluster2_l2>; |
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}; |
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cpu12: cpu@20300 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x20300>; |
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enable-method = "psci"; |
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next-level-cache = <&cluster3_l2>; |
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}; |
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cpu13: cpu@20301 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x20301>; |
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enable-method = "psci"; |
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next-level-cache = <&cluster3_l2>; |
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}; |
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cpu14: cpu@20302 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x20302>; |
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enable-method = "psci"; |
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next-level-cache = <&cluster3_l2>; |
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}; |
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cpu15: cpu@20303 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a57"; |
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reg = <0x20303>; |
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enable-method = "psci"; |
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next-level-cache = <&cluster3_l2>; |
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}; |
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cluster0_l2: l2-cache0 { |
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compatible = "cache"; |
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}; |
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cluster1_l2: l2-cache1 { |
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compatible = "cache"; |
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}; |
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cluster2_l2: l2-cache2 { |
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compatible = "cache"; |
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}; |
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cluster3_l2: l2-cache3 { |
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compatible = "cache"; |
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}; |
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}; |
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gic: interrupt-controller@8d000000 { |
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compatible = "arm,gic-v3"; |
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#interrupt-cells = <3>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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interrupt-controller; |
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#redistributor-regions = <1>; |
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redistributor-stride = <0x0 0x30000>; |
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reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ |
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<0x0 0x8d100000 0 0x300000>, /* GICR */ |
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<0x0 0xfe000000 0 0x10000>, /* GICC */ |
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<0x0 0xfe010000 0 0x10000>, /* GICH */ |
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<0x0 0xfe020000 0 0x10000>; /* GICV */ |
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
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its_peri: msi-controller@8c000000 { |
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compatible = "arm,gic-v3-its"; |
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msi-controller; |
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#msi-cells = <1>; |
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reg = <0x0 0x8c000000 0x0 0x40000>; |
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}; |
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its_m3: msi-controller@a3000000 { |
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compatible = "arm,gic-v3-its"; |
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msi-controller; |
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#msi-cells = <1>; |
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reg = <0x0 0xa3000000 0x0 0x40000>; |
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}; |
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its_pcie: msi-controller@b7000000 { |
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compatible = "arm,gic-v3-its"; |
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msi-controller; |
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#msi-cells = <1>; |
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reg = <0x0 0xb7000000 0x0 0x40000>; |
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}; |
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its_dsa: msi-controller@c6000000 { |
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compatible = "arm,gic-v3-its"; |
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msi-controller; |
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#msi-cells = <1>; |
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reg = <0x0 0xc6000000 0x0 0x40000>; |
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}; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
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}; |
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pmu { |
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compatible = "arm,cortex-a57-pmu"; |
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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soc { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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refclk200mhz: refclk200mhz { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <200000000>; |
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}; |
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uart0: serial@80300000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x0 0x80300000 0x0 0x10000>; |
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interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&refclk200mhz>, <&refclk200mhz>; |
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clock-names = "baudclk", "apb_pclk"; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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status = "disabled"; |
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}; |
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uart1: serial@80310000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x0 0x80310000 0x0 0x10000>; |
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interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&refclk200mhz>, <&refclk200mhz>; |
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clock-names = "baudclk", "apb_pclk"; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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status = "disabled"; |
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}; |
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lbc: local-bus@80380000 { |
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compatible = "hisilicon,hisi-localbus", "simple-bus"; |
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reg = <0x0 0x80380000 0x0 0x10000>; |
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status = "disabled"; |
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}; |
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peri_gpio0: gpio@802e0000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,dw-apb-gpio"; |
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reg = <0x0 0x802e0000 0x0 0x10000>; |
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status = "disabled"; |
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porta: gpio-controller@0 { |
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compatible = "snps,dw-apb-gpio-port"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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ngpios = <32>; |
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reg = <0>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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}; |
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peri_gpio1: gpio@802f0000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,dw-apb-gpio"; |
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reg = <0x0 0x802f0000 0x0 0x10000>; |
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status = "disabled"; |
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portb: gpio-controller@0 { |
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compatible = "snps,dw-apb-gpio-port"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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ngpios = <32>; |
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reg = <0>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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}; |
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}; |
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};
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