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351 lines
7.4 KiB
351 lines
7.4 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com) |
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*/ |
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/* |
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* Device Tree for ARC HS Development Kit |
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*/ |
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/dts-v1/; |
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/reset/snps,hsdk-reset.h> |
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/ { |
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model = "snps,hsdk"; |
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compatible = "snps,hsdk"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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chosen { |
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bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; |
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}; |
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aliases { |
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ethernet = &gmac; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu@0 { |
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device_type = "cpu"; |
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compatible = "snps,archs38"; |
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reg = <0>; |
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clocks = <&core_clk>; |
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}; |
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cpu@1 { |
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device_type = "cpu"; |
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compatible = "snps,archs38"; |
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reg = <1>; |
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clocks = <&core_clk>; |
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}; |
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cpu@2 { |
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device_type = "cpu"; |
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compatible = "snps,archs38"; |
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reg = <2>; |
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clocks = <&core_clk>; |
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}; |
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cpu@3 { |
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device_type = "cpu"; |
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compatible = "snps,archs38"; |
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reg = <3>; |
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clocks = <&core_clk>; |
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}; |
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}; |
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input_clk: input-clk { |
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#clock-cells = <0>; |
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compatible = "fixed-clock"; |
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clock-frequency = <33333333>; |
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}; |
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reg_5v0: regulator-5v0 { |
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compatible = "regulator-fixed"; |
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regulator-name = "5v0-supply"; |
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regulator-min-microvolt = <5000000>; |
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regulator-max-microvolt = <5000000>; |
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}; |
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cpu_intc: cpu-interrupt-controller { |
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compatible = "snps,archs-intc"; |
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interrupt-controller; |
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#interrupt-cells = <1>; |
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}; |
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idu_intc: idu-interrupt-controller { |
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compatible = "snps,archs-idu-intc"; |
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interrupt-controller; |
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#interrupt-cells = <1>; |
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interrupt-parent = <&cpu_intc>; |
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}; |
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arcpct: pct { |
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compatible = "snps,archs-pct"; |
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interrupt-parent = <&cpu_intc>; |
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interrupts = <20>; |
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}; |
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/* TIMER0 with interrupt for clockevent */ |
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timer { |
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compatible = "snps,arc-timer"; |
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interrupts = <16>; |
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interrupt-parent = <&cpu_intc>; |
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clocks = <&core_clk>; |
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}; |
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/* 64-bit Global Free Running Counter */ |
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gfrc { |
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compatible = "snps,archs-timer-gfrc"; |
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clocks = <&core_clk>; |
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}; |
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soc { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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interrupt-parent = <&idu_intc>; |
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ranges = <0x00000000 0x0 0xf0000000 0x10000000>; |
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cgu_rst: reset-controller@8a0 { |
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compatible = "snps,hsdk-reset"; |
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#reset-cells = <1>; |
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reg = <0x8a0 0x4>, <0xff0 0x4>; |
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}; |
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core_clk: core-clk@0 { |
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compatible = "snps,hsdk-core-pll-clock"; |
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reg = <0x00 0x10>, <0x14b8 0x4>; |
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#clock-cells = <0>; |
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clocks = <&input_clk>; |
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/* |
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* Set initial core pll output frequency to 1GHz. |
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* It will be applied at the core pll driver probing |
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* on early boot. |
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*/ |
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assigned-clocks = <&core_clk>; |
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assigned-clock-rates = <1000000000>; |
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}; |
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serial: serial@5000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x5000 0x100>; |
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clock-frequency = <33330000>; |
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interrupts = <6>; |
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baud = <115200>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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}; |
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gmacclk: gmacclk { |
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compatible = "fixed-clock"; |
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clock-frequency = <400000000>; |
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#clock-cells = <0>; |
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}; |
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mmcclk_ciu: mmcclk-ciu { |
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compatible = "fixed-clock"; |
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/* |
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* DW sdio controller has external ciu clock divider |
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* controlled via register in SDIO IP. Due to its |
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* unexpected default value (it should divide by 1 |
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* but it divides by 8) SDIO IP uses wrong clock and |
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* works unstable (see STAR 9001204800) |
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* We switched to the minimum possible value of the |
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* divisor (div-by-2) in HSDK platform code. |
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* So add temporary fix and change clock frequency |
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* to 50000000 Hz until we fix dw sdio driver itself. |
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*/ |
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clock-frequency = <50000000>; |
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#clock-cells = <0>; |
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}; |
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mmcclk_biu: mmcclk-biu { |
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compatible = "fixed-clock"; |
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clock-frequency = <400000000>; |
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#clock-cells = <0>; |
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}; |
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gpu_core_clk: gpu-core-clk { |
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compatible = "fixed-clock"; |
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clock-frequency = <400000000>; |
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#clock-cells = <0>; |
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}; |
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gpu_dma_clk: gpu-dma-clk { |
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compatible = "fixed-clock"; |
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clock-frequency = <400000000>; |
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#clock-cells = <0>; |
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}; |
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gpu_cfg_clk: gpu-cfg-clk { |
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compatible = "fixed-clock"; |
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clock-frequency = <200000000>; |
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#clock-cells = <0>; |
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}; |
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dmac_core_clk: dmac-core-clk { |
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compatible = "fixed-clock"; |
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clock-frequency = <400000000>; |
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#clock-cells = <0>; |
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}; |
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dmac_cfg_clk: dmac-gpu-cfg-clk { |
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compatible = "fixed-clock"; |
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clock-frequency = <200000000>; |
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#clock-cells = <0>; |
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}; |
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gmac: ethernet@8000 { |
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#interrupt-cells = <1>; |
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compatible = "snps,dwmac"; |
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reg = <0x8000 0x2000>; |
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interrupts = <10>; |
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interrupt-names = "macirq"; |
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phy-mode = "rgmii-id"; |
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snps,pbl = <32>; |
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snps,multicast-filter-bins = <256>; |
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clocks = <&gmacclk>; |
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clock-names = "stmmaceth"; |
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phy-handle = <&phy0>; |
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resets = <&cgu_rst HSDK_ETH_RESET>; |
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reset-names = "stmmaceth"; |
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mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */ |
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dma-coherent; |
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tx-fifo-depth = <4096>; |
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rx-fifo-depth = <4096>; |
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mdio { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,dwmac-mdio"; |
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phy0: ethernet-phy@0 { /* Micrel KSZ9031 */ |
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reg = <0>; |
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}; |
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}; |
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}; |
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ohci@60000 { |
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compatible = "snps,hsdk-v1.0-ohci", "generic-ohci"; |
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reg = <0x60000 0x100>; |
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interrupts = <15>; |
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resets = <&cgu_rst HSDK_USB_RESET>; |
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dma-coherent; |
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}; |
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ehci@40000 { |
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compatible = "snps,hsdk-v1.0-ehci", "generic-ehci"; |
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reg = <0x40000 0x100>; |
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interrupts = <15>; |
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resets = <&cgu_rst HSDK_USB_RESET>; |
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dma-coherent; |
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}; |
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mmc@a000 { |
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compatible = "altr,socfpga-dw-mshc"; |
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reg = <0xa000 0x400>; |
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num-slots = <1>; |
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fifo-depth = <16>; |
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card-detect-delay = <200>; |
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clocks = <&mmcclk_biu>, <&mmcclk_ciu>; |
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clock-names = "biu", "ciu"; |
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interrupts = <12>; |
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bus-width = <4>; |
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dma-coherent; |
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}; |
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spi0: spi@20000 { |
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compatible = "snps,dw-apb-ssi"; |
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reg = <0x20000 0x100>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupts = <16>; |
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num-cs = <2>; |
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reg-io-width = <4>; |
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clocks = <&input_clk>; |
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cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>, |
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<&creg_gpio 1 GPIO_ACTIVE_LOW>; |
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spi-flash@0 { |
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compatible = "sst26wf016b", "jedec,spi-nor"; |
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reg = <0>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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spi-max-frequency = <4000000>; |
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}; |
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adc@1 { |
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compatible = "ti,adc108s102"; |
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reg = <1>; |
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vref-supply = <®_5v0>; |
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spi-max-frequency = <1000000>; |
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}; |
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}; |
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creg_gpio: gpio@14b0 { |
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compatible = "snps,creg-gpio-hsdk"; |
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reg = <0x14b0 0x4>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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ngpios = <2>; |
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}; |
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gpio: gpio@3000 { |
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compatible = "snps,dw-apb-gpio"; |
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reg = <0x3000 0x20>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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gpio_port_a: gpio-controller@0 { |
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compatible = "snps,dw-apb-gpio-port"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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snps,nr-gpios = <24>; |
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reg = <0>; |
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}; |
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}; |
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gpu_3d: gpu@90000 { |
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compatible = "vivante,gc"; |
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reg = <0x90000 0x4000>; |
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clocks = <&gpu_dma_clk>, |
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<&gpu_cfg_clk>, |
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<&gpu_core_clk>, |
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<&gpu_core_clk>; |
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clock-names = "bus", "reg", "core", "shader"; |
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interrupts = <28>; |
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}; |
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dmac: dmac@80000 { |
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compatible = "snps,axi-dma-1.01a"; |
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reg = <0x80000 0x400>; |
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interrupts = <27>; |
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clocks = <&dmac_core_clk>, <&dmac_cfg_clk>; |
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clock-names = "core-clk", "cfgr-clk"; |
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dma-channels = <4>; |
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snps,dma-masters = <2>; |
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snps,data-width = <3>; |
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snps,block-size = <4096 4096 4096 4096>; |
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snps,priority = <0 1 2 3>; |
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snps,axi-max-burst-len = <16>; |
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}; |
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}; |
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memory@80000000 { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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device_type = "memory"; |
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reg = <0x0 0x80000000 0x0 0x40000000>; /* 1 GB lowmem */ |
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/* 0x1 0x00000000 0x0 0x40000000>; 1 GB highmem */ |
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}; |
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};
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