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243 lines
5.7 KiB
243 lines
5.7 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Abilis Systems TB10X SOC device tree |
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* |
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* Copyright (C) Abilis Systems 2013 |
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* |
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* Author: Christian Ruppert <[email protected]> |
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*/ |
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/ { |
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compatible = "abilis,arc-tb10x"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu@0 { |
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device_type = "cpu"; |
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compatible = "snps,arc770d"; |
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reg = <0>; |
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}; |
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}; |
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/* TIMER0 with interrupt for clockevent */ |
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timer0 { |
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compatible = "snps,arc-timer"; |
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interrupts = <3>; |
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interrupt-parent = <&intc>; |
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clocks = <&cpu_clk>; |
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}; |
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/* TIMER1 for free running clocksource */ |
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timer1 { |
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compatible = "snps,arc-timer"; |
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clocks = <&cpu_clk>; |
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}; |
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soc100 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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device_type = "soc"; |
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ranges = <0xfe000000 0xfe000000 0x02000000 |
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0x000f0000 0x000f0000 0x00010000>; |
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compatible = "abilis,tb10x", "simple-bus"; |
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pll0: oscillator { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-output-names = "pll0"; |
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}; |
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cpu_clk: clkdiv_cpu { |
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compatible = "fixed-factor-clock"; |
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#clock-cells = <0>; |
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clocks = <&pll0>; |
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clock-output-names = "cpu_clk"; |
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}; |
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ahb_clk: clkdiv_ahb { |
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compatible = "fixed-factor-clock"; |
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#clock-cells = <0>; |
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clocks = <&pll0>; |
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clock-output-names = "ahb_clk"; |
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}; |
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iomux: iomux@ff10601c { |
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compatible = "abilis,tb10x-iomux"; |
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#gpio-range-cells = <3>; |
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reg = <0xff10601c 0x4>; |
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}; |
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intc: interrupt-controller { |
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compatible = "snps,arc700-intc"; |
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interrupt-controller; |
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#interrupt-cells = <1>; |
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}; |
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tb10x_ictl: pic@fe002000 { |
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compatible = "abilis,tb10x-ictl"; |
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reg = <0xfe002000 0x20>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupt-parent = <&intc>; |
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interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 |
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20 21 22 23 24 25 26 27 28 29 30 31>; |
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}; |
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uart@ff100000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0xff100000 0x100>; |
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clock-frequency = <166666666>; |
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interrupts = <25 8>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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interrupt-parent = <&tb10x_ictl>; |
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}; |
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ethernet@fe100000 { |
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compatible = "snps,dwmac-3.70a","snps,dwmac"; |
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reg = <0xfe100000 0x1058>; |
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interrupt-parent = <&tb10x_ictl>; |
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interrupts = <6 8>; |
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interrupt-names = "macirq"; |
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clocks = <&ahb_clk>; |
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clock-names = "stmmaceth"; |
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}; |
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dma@fe000000 { |
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compatible = "snps,dma-spear1340"; |
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reg = <0xfe000000 0x400>; |
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interrupt-parent = <&tb10x_ictl>; |
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interrupts = <14 8>; |
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dma-channels = <6>; |
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dma-requests = <0>; |
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dma-masters = <1>; |
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#dma-cells = <3>; |
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chan_allocation_order = <0>; |
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chan_priority = <1>; |
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block_size = <0x7ff>; |
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data-width = <4>; |
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clocks = <&ahb_clk>; |
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clock-names = "hclk"; |
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multi-block = <1 1 1 1 1 1>; |
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}; |
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i2c0: i2c@ff120000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,designware-i2c"; |
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reg = <0xff120000 0x1000>; |
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interrupt-parent = <&tb10x_ictl>; |
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interrupts = <12 8>; |
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clocks = <&ahb_clk>; |
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}; |
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i2c1: i2c@ff121000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,designware-i2c"; |
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reg = <0xff121000 0x1000>; |
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interrupt-parent = <&tb10x_ictl>; |
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interrupts = <12 8>; |
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clocks = <&ahb_clk>; |
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}; |
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i2c2: i2c@ff122000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,designware-i2c"; |
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reg = <0xff122000 0x1000>; |
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interrupt-parent = <&tb10x_ictl>; |
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interrupts = <12 8>; |
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clocks = <&ahb_clk>; |
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}; |
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i2c3: i2c@ff123000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,designware-i2c"; |
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reg = <0xff123000 0x1000>; |
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interrupt-parent = <&tb10x_ictl>; |
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interrupts = <12 8>; |
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clocks = <&ahb_clk>; |
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}; |
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i2c4: i2c@ff124000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,designware-i2c"; |
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reg = <0xff124000 0x1000>; |
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interrupt-parent = <&tb10x_ictl>; |
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interrupts = <12 8>; |
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clocks = <&ahb_clk>; |
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}; |
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spi0: spi@fe010000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cell-index = <0>; |
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compatible = "abilis,tb100-spi"; |
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num-cs = <1>; |
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reg = <0xfe010000 0x20>; |
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interrupt-parent = <&tb10x_ictl>; |
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interrupts = <26 8>; |
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clocks = <&ahb_clk>; |
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}; |
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spi1: spi@fe011000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cell-index = <1>; |
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compatible = "abilis,tb100-spi"; |
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num-cs = <2>; |
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reg = <0xfe011000 0x20>; |
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interrupt-parent = <&tb10x_ictl>; |
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interrupts = <10 8>; |
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clocks = <&ahb_clk>; |
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}; |
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tb10x_tsm: tb10x-tsm@ff316000 { |
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compatible = "abilis,tb100-tsm"; |
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reg = <0xff316000 0x400>; |
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interrupt-parent = <&tb10x_ictl>; |
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interrupts = <17 8>; |
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output-clkdiv = <4>; |
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global-packet-delay = <0x21>; |
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port-packet-delay = <0>; |
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}; |
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tb10x_stream_proc: tb10x-stream-proc { |
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compatible = "abilis,tb100-streamproc"; |
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reg = <0xfff00000 0x200>, |
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<0x000f0000 0x10000>, |
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<0xfff00200 0x105>, |
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<0xff10600c 0x1>, |
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<0xfe001018 0x1>; |
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reg-names = "mbox", |
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"sp_iccm", |
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"mbox_irq", |
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"cpuctrl", |
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"a6it_int_force"; |
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interrupt-parent = <&tb10x_ictl>; |
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interrupts = <20 2>, <19 2>; |
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interrupt-names = "cmd_irq", "event_irq"; |
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}; |
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tb10x_mdsc0: tb10x-mdscr@ff300000 { |
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compatible = "abilis,tb100-mdscr"; |
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reg = <0xff300000 0x7000>; |
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tb100-mdscr-manage-tsin; |
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}; |
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tb10x_mscr0: tb10x-mdscr@ff307000 { |
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compatible = "abilis,tb100-mdscr"; |
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reg = <0xff307000 0x7000>; |
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}; |
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tb10x_scr0: tb10x-mdscr@ff30e000 { |
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compatible = "abilis,tb100-mdscr"; |
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reg = <0xff30e000 0x4000>; |
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tb100-mdscr-manage-tsin; |
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}; |
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tb10x_scr1: tb10x-mdscr@ff312000 { |
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compatible = "abilis,tb100-mdscr"; |
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reg = <0xff312000 0x4000>; |
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tb100-mdscr-manage-tsin; |
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}; |
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tb10x_wfb: tb10x-wfb@ff319000 { |
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compatible = "abilis,tb100-wfb"; |
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reg = <0xff319000 0x1000>; |
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interrupt-parent = <&tb10x_ictl>; |
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interrupts = <16 8>; |
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}; |
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}; |
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};
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