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1773 lines
53 KiB
1773 lines
53 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. |
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// Copyright (c) 2018, Linaro Limited |
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#include <linux/slab.h> |
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#include <linux/kernel.h> |
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#include <linux/uaccess.h> |
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#include <linux/wait.h> |
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#include <linux/jiffies.h> |
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#include <linux/sched.h> |
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#include <linux/module.h> |
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#include <linux/kref.h> |
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#include <linux/of.h> |
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#include <linux/of_platform.h> |
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#include <linux/spinlock.h> |
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#include <linux/delay.h> |
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#include <linux/soc/qcom/apr.h> |
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#include <sound/soc.h> |
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#include <sound/soc-dai.h> |
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#include <sound/pcm.h> |
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#include <sound/pcm_params.h> |
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#include "q6dsp-errno.h" |
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#include "q6core.h" |
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#include "q6afe.h" |
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/* AFE CMDs */ |
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#define AFE_PORT_CMD_DEVICE_START 0x000100E5 |
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#define AFE_PORT_CMD_DEVICE_STOP 0x000100E6 |
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#define AFE_PORT_CMD_SET_PARAM_V2 0x000100EF |
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#define AFE_SVC_CMD_SET_PARAM 0x000100f3 |
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#define AFE_PORT_CMDRSP_GET_PARAM_V2 0x00010106 |
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#define AFE_PARAM_ID_HDMI_CONFIG 0x00010210 |
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#define AFE_MODULE_AUDIO_DEV_INTERFACE 0x0001020C |
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#define AFE_MODULE_TDM 0x0001028A |
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#define AFE_PARAM_ID_CDC_SLIMBUS_SLAVE_CFG 0x00010235 |
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#define AFE_PARAM_ID_LPAIF_CLK_CONFIG 0x00010238 |
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#define AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG 0x00010239 |
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#define AFE_PARAM_ID_SLIMBUS_CONFIG 0x00010212 |
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#define AFE_PARAM_ID_I2S_CONFIG 0x0001020D |
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#define AFE_PARAM_ID_TDM_CONFIG 0x0001029D |
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#define AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG 0x00010297 |
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#define AFE_PARAM_ID_CODEC_DMA_CONFIG 0x000102B8 |
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#define AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST 0x000100f4 |
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#define AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST 0x000100f5 |
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#define AFE_CMD_REMOTE_LPASS_CORE_HW_DEVOTE_REQUEST 0x000100f6 |
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/* I2S config specific */ |
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#define AFE_API_VERSION_I2S_CONFIG 0x1 |
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#define AFE_PORT_I2S_SD0 0x1 |
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#define AFE_PORT_I2S_SD1 0x2 |
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#define AFE_PORT_I2S_SD2 0x3 |
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#define AFE_PORT_I2S_SD3 0x4 |
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#define AFE_PORT_I2S_SD0_MASK BIT(0x0) |
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#define AFE_PORT_I2S_SD1_MASK BIT(0x1) |
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#define AFE_PORT_I2S_SD2_MASK BIT(0x2) |
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#define AFE_PORT_I2S_SD3_MASK BIT(0x3) |
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#define AFE_PORT_I2S_SD0_1_MASK GENMASK(1, 0) |
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#define AFE_PORT_I2S_SD2_3_MASK GENMASK(3, 2) |
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#define AFE_PORT_I2S_SD0_1_2_MASK GENMASK(2, 0) |
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#define AFE_PORT_I2S_SD0_1_2_3_MASK GENMASK(3, 0) |
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#define AFE_PORT_I2S_QUAD01 0x5 |
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#define AFE_PORT_I2S_QUAD23 0x6 |
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#define AFE_PORT_I2S_6CHS 0x7 |
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#define AFE_PORT_I2S_8CHS 0x8 |
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#define AFE_PORT_I2S_MONO 0x0 |
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#define AFE_PORT_I2S_STEREO 0x1 |
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#define AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL 0x0 |
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#define AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL 0x1 |
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#define AFE_LINEAR_PCM_DATA 0x0 |
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/* Port IDs */ |
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#define AFE_API_VERSION_HDMI_CONFIG 0x1 |
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#define AFE_PORT_ID_MULTICHAN_HDMI_RX 0x100E |
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#define AFE_PORT_ID_HDMI_OVER_DP_RX 0x6020 |
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#define AFE_API_VERSION_SLIMBUS_CONFIG 0x1 |
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/* Clock set API version */ |
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#define AFE_API_VERSION_CLOCK_SET 1 |
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#define Q6AFE_LPASS_CLK_CONFIG_API_VERSION 0x1 |
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#define AFE_MODULE_CLOCK_SET 0x0001028F |
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#define AFE_PARAM_ID_CLOCK_SET 0x00010290 |
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/* SLIMbus Rx port on channel 0. */ |
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#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX 0x4000 |
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/* SLIMbus Tx port on channel 0. */ |
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#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX 0x4001 |
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/* SLIMbus Rx port on channel 1. */ |
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#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX 0x4002 |
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/* SLIMbus Tx port on channel 1. */ |
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#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX 0x4003 |
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/* SLIMbus Rx port on channel 2. */ |
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#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX 0x4004 |
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/* SLIMbus Tx port on channel 2. */ |
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#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX 0x4005 |
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/* SLIMbus Rx port on channel 3. */ |
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#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX 0x4006 |
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/* SLIMbus Tx port on channel 3. */ |
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#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX 0x4007 |
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/* SLIMbus Rx port on channel 4. */ |
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#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX 0x4008 |
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/* SLIMbus Tx port on channel 4. */ |
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#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX 0x4009 |
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/* SLIMbus Rx port on channel 5. */ |
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#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX 0x400a |
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/* SLIMbus Tx port on channel 5. */ |
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#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX 0x400b |
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/* SLIMbus Rx port on channel 6. */ |
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#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX 0x400c |
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/* SLIMbus Tx port on channel 6. */ |
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#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX 0x400d |
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#define AFE_PORT_ID_PRIMARY_MI2S_RX 0x1000 |
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#define AFE_PORT_ID_PRIMARY_MI2S_TX 0x1001 |
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#define AFE_PORT_ID_SECONDARY_MI2S_RX 0x1002 |
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#define AFE_PORT_ID_SECONDARY_MI2S_TX 0x1003 |
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#define AFE_PORT_ID_TERTIARY_MI2S_RX 0x1004 |
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#define AFE_PORT_ID_TERTIARY_MI2S_TX 0x1005 |
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#define AFE_PORT_ID_QUATERNARY_MI2S_RX 0x1006 |
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#define AFE_PORT_ID_QUATERNARY_MI2S_TX 0x1007 |
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#define AFE_PORT_ID_QUINARY_MI2S_RX 0x1016 |
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#define AFE_PORT_ID_QUINARY_MI2S_TX 0x1017 |
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/* Start of the range of port IDs for TDM devices. */ |
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#define AFE_PORT_ID_TDM_PORT_RANGE_START 0x9000 |
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/* End of the range of port IDs for TDM devices. */ |
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#define AFE_PORT_ID_TDM_PORT_RANGE_END \ |
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(AFE_PORT_ID_TDM_PORT_RANGE_START+0x50-1) |
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/* Size of the range of port IDs for TDM ports. */ |
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#define AFE_PORT_ID_TDM_PORT_RANGE_SIZE \ |
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(AFE_PORT_ID_TDM_PORT_RANGE_END - \ |
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AFE_PORT_ID_TDM_PORT_RANGE_START+1) |
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#define AFE_PORT_ID_PRIMARY_TDM_RX \ |
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x00) |
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#define AFE_PORT_ID_PRIMARY_TDM_RX_1 \ |
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(AFE_PORT_ID_PRIMARY_TDM_RX + 0x02) |
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#define AFE_PORT_ID_PRIMARY_TDM_RX_2 \ |
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(AFE_PORT_ID_PRIMARY_TDM_RX + 0x04) |
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#define AFE_PORT_ID_PRIMARY_TDM_RX_3 \ |
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(AFE_PORT_ID_PRIMARY_TDM_RX + 0x06) |
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#define AFE_PORT_ID_PRIMARY_TDM_RX_4 \ |
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(AFE_PORT_ID_PRIMARY_TDM_RX + 0x08) |
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#define AFE_PORT_ID_PRIMARY_TDM_RX_5 \ |
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(AFE_PORT_ID_PRIMARY_TDM_RX + 0x0A) |
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#define AFE_PORT_ID_PRIMARY_TDM_RX_6 \ |
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(AFE_PORT_ID_PRIMARY_TDM_RX + 0x0C) |
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#define AFE_PORT_ID_PRIMARY_TDM_RX_7 \ |
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(AFE_PORT_ID_PRIMARY_TDM_RX + 0x0E) |
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#define AFE_PORT_ID_PRIMARY_TDM_TX \ |
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x01) |
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#define AFE_PORT_ID_PRIMARY_TDM_TX_1 \ |
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(AFE_PORT_ID_PRIMARY_TDM_TX + 0x02) |
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#define AFE_PORT_ID_PRIMARY_TDM_TX_2 \ |
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(AFE_PORT_ID_PRIMARY_TDM_TX + 0x04) |
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#define AFE_PORT_ID_PRIMARY_TDM_TX_3 \ |
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(AFE_PORT_ID_PRIMARY_TDM_TX + 0x06) |
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#define AFE_PORT_ID_PRIMARY_TDM_TX_4 \ |
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(AFE_PORT_ID_PRIMARY_TDM_TX + 0x08) |
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#define AFE_PORT_ID_PRIMARY_TDM_TX_5 \ |
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(AFE_PORT_ID_PRIMARY_TDM_TX + 0x0A) |
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#define AFE_PORT_ID_PRIMARY_TDM_TX_6 \ |
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(AFE_PORT_ID_PRIMARY_TDM_TX + 0x0C) |
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#define AFE_PORT_ID_PRIMARY_TDM_TX_7 \ |
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(AFE_PORT_ID_PRIMARY_TDM_TX + 0x0E) |
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#define AFE_PORT_ID_SECONDARY_TDM_RX \ |
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x10) |
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#define AFE_PORT_ID_SECONDARY_TDM_RX_1 \ |
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(AFE_PORT_ID_SECONDARY_TDM_RX + 0x02) |
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#define AFE_PORT_ID_SECONDARY_TDM_RX_2 \ |
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(AFE_PORT_ID_SECONDARY_TDM_RX + 0x04) |
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#define AFE_PORT_ID_SECONDARY_TDM_RX_3 \ |
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(AFE_PORT_ID_SECONDARY_TDM_RX + 0x06) |
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#define AFE_PORT_ID_SECONDARY_TDM_RX_4 \ |
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(AFE_PORT_ID_SECONDARY_TDM_RX + 0x08) |
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#define AFE_PORT_ID_SECONDARY_TDM_RX_5 \ |
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(AFE_PORT_ID_SECONDARY_TDM_RX + 0x0A) |
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#define AFE_PORT_ID_SECONDARY_TDM_RX_6 \ |
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(AFE_PORT_ID_SECONDARY_TDM_RX + 0x0C) |
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#define AFE_PORT_ID_SECONDARY_TDM_RX_7 \ |
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(AFE_PORT_ID_SECONDARY_TDM_RX + 0x0E) |
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#define AFE_PORT_ID_SECONDARY_TDM_TX \ |
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x11) |
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#define AFE_PORT_ID_SECONDARY_TDM_TX_1 \ |
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(AFE_PORT_ID_SECONDARY_TDM_TX + 0x02) |
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#define AFE_PORT_ID_SECONDARY_TDM_TX_2 \ |
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(AFE_PORT_ID_SECONDARY_TDM_TX + 0x04) |
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#define AFE_PORT_ID_SECONDARY_TDM_TX_3 \ |
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(AFE_PORT_ID_SECONDARY_TDM_TX + 0x06) |
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#define AFE_PORT_ID_SECONDARY_TDM_TX_4 \ |
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(AFE_PORT_ID_SECONDARY_TDM_TX + 0x08) |
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#define AFE_PORT_ID_SECONDARY_TDM_TX_5 \ |
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(AFE_PORT_ID_SECONDARY_TDM_TX + 0x0A) |
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#define AFE_PORT_ID_SECONDARY_TDM_TX_6 \ |
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(AFE_PORT_ID_SECONDARY_TDM_TX + 0x0C) |
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#define AFE_PORT_ID_SECONDARY_TDM_TX_7 \ |
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(AFE_PORT_ID_SECONDARY_TDM_TX + 0x0E) |
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#define AFE_PORT_ID_TERTIARY_TDM_RX \ |
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x20) |
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#define AFE_PORT_ID_TERTIARY_TDM_RX_1 \ |
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(AFE_PORT_ID_TERTIARY_TDM_RX + 0x02) |
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#define AFE_PORT_ID_TERTIARY_TDM_RX_2 \ |
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(AFE_PORT_ID_TERTIARY_TDM_RX + 0x04) |
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#define AFE_PORT_ID_TERTIARY_TDM_RX_3 \ |
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(AFE_PORT_ID_TERTIARY_TDM_RX + 0x06) |
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#define AFE_PORT_ID_TERTIARY_TDM_RX_4 \ |
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(AFE_PORT_ID_TERTIARY_TDM_RX + 0x08) |
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#define AFE_PORT_ID_TERTIARY_TDM_RX_5 \ |
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(AFE_PORT_ID_TERTIARY_TDM_RX + 0x0A) |
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#define AFE_PORT_ID_TERTIARY_TDM_RX_6 \ |
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(AFE_PORT_ID_TERTIARY_TDM_RX + 0x0C) |
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#define AFE_PORT_ID_TERTIARY_TDM_RX_7 \ |
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(AFE_PORT_ID_TERTIARY_TDM_RX + 0x0E) |
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#define AFE_PORT_ID_TERTIARY_TDM_TX \ |
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x21) |
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#define AFE_PORT_ID_TERTIARY_TDM_TX_1 \ |
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(AFE_PORT_ID_TERTIARY_TDM_TX + 0x02) |
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#define AFE_PORT_ID_TERTIARY_TDM_TX_2 \ |
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(AFE_PORT_ID_TERTIARY_TDM_TX + 0x04) |
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#define AFE_PORT_ID_TERTIARY_TDM_TX_3 \ |
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(AFE_PORT_ID_TERTIARY_TDM_TX + 0x06) |
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#define AFE_PORT_ID_TERTIARY_TDM_TX_4 \ |
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(AFE_PORT_ID_TERTIARY_TDM_TX + 0x08) |
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#define AFE_PORT_ID_TERTIARY_TDM_TX_5 \ |
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(AFE_PORT_ID_TERTIARY_TDM_TX + 0x0A) |
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#define AFE_PORT_ID_TERTIARY_TDM_TX_6 \ |
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(AFE_PORT_ID_TERTIARY_TDM_TX + 0x0C) |
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#define AFE_PORT_ID_TERTIARY_TDM_TX_7 \ |
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(AFE_PORT_ID_TERTIARY_TDM_TX + 0x0E) |
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#define AFE_PORT_ID_QUATERNARY_TDM_RX \ |
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x30) |
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#define AFE_PORT_ID_QUATERNARY_TDM_RX_1 \ |
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(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x02) |
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#define AFE_PORT_ID_QUATERNARY_TDM_RX_2 \ |
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(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x04) |
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#define AFE_PORT_ID_QUATERNARY_TDM_RX_3 \ |
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(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x06) |
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#define AFE_PORT_ID_QUATERNARY_TDM_RX_4 \ |
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(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x08) |
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#define AFE_PORT_ID_QUATERNARY_TDM_RX_5 \ |
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(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0A) |
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#define AFE_PORT_ID_QUATERNARY_TDM_RX_6 \ |
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(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0C) |
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#define AFE_PORT_ID_QUATERNARY_TDM_RX_7 \ |
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(AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0E) |
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#define AFE_PORT_ID_QUATERNARY_TDM_TX \ |
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x31) |
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#define AFE_PORT_ID_QUATERNARY_TDM_TX_1 \ |
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(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x02) |
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#define AFE_PORT_ID_QUATERNARY_TDM_TX_2 \ |
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(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x04) |
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#define AFE_PORT_ID_QUATERNARY_TDM_TX_3 \ |
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(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x06) |
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#define AFE_PORT_ID_QUATERNARY_TDM_TX_4 \ |
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(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x08) |
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#define AFE_PORT_ID_QUATERNARY_TDM_TX_5 \ |
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(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0A) |
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#define AFE_PORT_ID_QUATERNARY_TDM_TX_6 \ |
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(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0C) |
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#define AFE_PORT_ID_QUATERNARY_TDM_TX_7 \ |
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(AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0E) |
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#define AFE_PORT_ID_QUINARY_TDM_RX \ |
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x40) |
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#define AFE_PORT_ID_QUINARY_TDM_RX_1 \ |
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(AFE_PORT_ID_QUINARY_TDM_RX + 0x02) |
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#define AFE_PORT_ID_QUINARY_TDM_RX_2 \ |
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(AFE_PORT_ID_QUINARY_TDM_RX + 0x04) |
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#define AFE_PORT_ID_QUINARY_TDM_RX_3 \ |
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(AFE_PORT_ID_QUINARY_TDM_RX + 0x06) |
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#define AFE_PORT_ID_QUINARY_TDM_RX_4 \ |
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(AFE_PORT_ID_QUINARY_TDM_RX + 0x08) |
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#define AFE_PORT_ID_QUINARY_TDM_RX_5 \ |
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(AFE_PORT_ID_QUINARY_TDM_RX + 0x0A) |
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#define AFE_PORT_ID_QUINARY_TDM_RX_6 \ |
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(AFE_PORT_ID_QUINARY_TDM_RX + 0x0C) |
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#define AFE_PORT_ID_QUINARY_TDM_RX_7 \ |
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(AFE_PORT_ID_QUINARY_TDM_RX + 0x0E) |
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#define AFE_PORT_ID_QUINARY_TDM_TX \ |
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(AFE_PORT_ID_TDM_PORT_RANGE_START + 0x41) |
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#define AFE_PORT_ID_QUINARY_TDM_TX_1 \ |
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(AFE_PORT_ID_QUINARY_TDM_TX + 0x02) |
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#define AFE_PORT_ID_QUINARY_TDM_TX_2 \ |
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(AFE_PORT_ID_QUINARY_TDM_TX + 0x04) |
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#define AFE_PORT_ID_QUINARY_TDM_TX_3 \ |
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(AFE_PORT_ID_QUINARY_TDM_TX + 0x06) |
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#define AFE_PORT_ID_QUINARY_TDM_TX_4 \ |
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(AFE_PORT_ID_QUINARY_TDM_TX + 0x08) |
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#define AFE_PORT_ID_QUINARY_TDM_TX_5 \ |
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(AFE_PORT_ID_QUINARY_TDM_TX + 0x0A) |
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#define AFE_PORT_ID_QUINARY_TDM_TX_6 \ |
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(AFE_PORT_ID_QUINARY_TDM_TX + 0x0C) |
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#define AFE_PORT_ID_QUINARY_TDM_TX_7 \ |
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(AFE_PORT_ID_QUINARY_TDM_TX + 0x0E) |
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/* AFE WSA Codec DMA Rx port 0 */ |
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#define AFE_PORT_ID_WSA_CODEC_DMA_RX_0 0xB000 |
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/* AFE WSA Codec DMA Tx port 0 */ |
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#define AFE_PORT_ID_WSA_CODEC_DMA_TX_0 0xB001 |
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/* AFE WSA Codec DMA Rx port 1 */ |
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#define AFE_PORT_ID_WSA_CODEC_DMA_RX_1 0xB002 |
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/* AFE WSA Codec DMA Tx port 1 */ |
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#define AFE_PORT_ID_WSA_CODEC_DMA_TX_1 0xB003 |
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/* AFE WSA Codec DMA Tx port 2 */ |
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#define AFE_PORT_ID_WSA_CODEC_DMA_TX_2 0xB005 |
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/* AFE VA Codec DMA Tx port 0 */ |
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#define AFE_PORT_ID_VA_CODEC_DMA_TX_0 0xB021 |
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/* AFE VA Codec DMA Tx port 1 */ |
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#define AFE_PORT_ID_VA_CODEC_DMA_TX_1 0xB023 |
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/* AFE VA Codec DMA Tx port 2 */ |
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#define AFE_PORT_ID_VA_CODEC_DMA_TX_2 0xB025 |
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/* AFE Rx Codec DMA Rx port 0 */ |
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#define AFE_PORT_ID_RX_CODEC_DMA_RX_0 0xB030 |
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/* AFE Tx Codec DMA Tx port 0 */ |
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#define AFE_PORT_ID_TX_CODEC_DMA_TX_0 0xB031 |
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/* AFE Rx Codec DMA Rx port 1 */ |
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#define AFE_PORT_ID_RX_CODEC_DMA_RX_1 0xB032 |
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/* AFE Tx Codec DMA Tx port 1 */ |
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#define AFE_PORT_ID_TX_CODEC_DMA_TX_1 0xB033 |
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/* AFE Rx Codec DMA Rx port 2 */ |
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#define AFE_PORT_ID_RX_CODEC_DMA_RX_2 0xB034 |
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/* AFE Tx Codec DMA Tx port 2 */ |
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#define AFE_PORT_ID_TX_CODEC_DMA_TX_2 0xB035 |
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/* AFE Rx Codec DMA Rx port 3 */ |
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#define AFE_PORT_ID_RX_CODEC_DMA_RX_3 0xB036 |
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/* AFE Tx Codec DMA Tx port 3 */ |
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#define AFE_PORT_ID_TX_CODEC_DMA_TX_3 0xB037 |
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/* AFE Rx Codec DMA Rx port 4 */ |
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#define AFE_PORT_ID_RX_CODEC_DMA_RX_4 0xB038 |
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/* AFE Tx Codec DMA Tx port 4 */ |
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#define AFE_PORT_ID_TX_CODEC_DMA_TX_4 0xB039 |
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/* AFE Rx Codec DMA Rx port 5 */ |
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#define AFE_PORT_ID_RX_CODEC_DMA_RX_5 0xB03A |
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/* AFE Tx Codec DMA Tx port 5 */ |
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#define AFE_PORT_ID_TX_CODEC_DMA_TX_5 0xB03B |
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/* AFE Rx Codec DMA Rx port 6 */ |
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#define AFE_PORT_ID_RX_CODEC_DMA_RX_6 0xB03C |
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/* AFE Rx Codec DMA Rx port 7 */ |
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#define AFE_PORT_ID_RX_CODEC_DMA_RX_7 0xB03E |
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#define Q6AFE_LPASS_MODE_CLK1_VALID 1 |
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#define Q6AFE_LPASS_MODE_CLK2_VALID 2 |
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#define Q6AFE_LPASS_CLK_SRC_INTERNAL 1 |
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#define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0 |
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#define AFE_API_VERSION_TDM_CONFIG 1 |
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#define AFE_API_VERSION_SLOT_MAPPING_CONFIG 1 |
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#define AFE_API_VERSION_CODEC_DMA_CONFIG 1 |
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#define TIMEOUT_MS 1000 |
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#define AFE_CMD_RESP_AVAIL 0 |
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#define AFE_CMD_RESP_NONE 1 |
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#define AFE_CLK_TOKEN 1024 |
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struct q6afe { |
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struct apr_device *apr; |
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struct device *dev; |
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struct q6core_svc_api_info ainfo; |
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struct mutex lock; |
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struct aprv2_ibasic_rsp_result_t result; |
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wait_queue_head_t wait; |
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struct list_head port_list; |
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spinlock_t port_list_lock; |
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}; |
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struct afe_port_cmd_device_start { |
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u16 port_id; |
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u16 reserved; |
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} __packed; |
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struct afe_port_cmd_device_stop { |
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u16 port_id; |
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u16 reserved; |
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/* Reserved for 32-bit alignment. This field must be set to 0.*/ |
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} __packed; |
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struct afe_port_param_data_v2 { |
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u32 module_id; |
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u32 param_id; |
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u16 param_size; |
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u16 reserved; |
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} __packed; |
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struct afe_svc_cmd_set_param { |
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uint32_t payload_size; |
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uint32_t payload_address_lsw; |
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uint32_t payload_address_msw; |
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uint32_t mem_map_handle; |
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} __packed; |
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struct afe_port_cmd_set_param_v2 { |
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u16 port_id; |
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u16 payload_size; |
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u32 payload_address_lsw; |
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u32 payload_address_msw; |
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u32 mem_map_handle; |
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} __packed; |
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struct afe_param_id_hdmi_multi_chan_audio_cfg { |
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u32 hdmi_cfg_minor_version; |
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u16 datatype; |
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u16 channel_allocation; |
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u32 sample_rate; |
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u16 bit_width; |
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u16 reserved; |
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} __packed; |
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struct afe_param_id_slimbus_cfg { |
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u32 sb_cfg_minor_version; |
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/* Minor version used for tracking the version of the SLIMBUS |
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* configuration interface. |
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* Supported values: #AFE_API_VERSION_SLIMBUS_CONFIG |
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*/ |
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u16 slimbus_dev_id; |
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/* SLIMbus hardware device ID, which is required to handle |
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* multiple SLIMbus hardware blocks. |
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* Supported values: - #AFE_SLIMBUS_DEVICE_1 - #AFE_SLIMBUS_DEVICE_2 |
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*/ |
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u16 bit_width; |
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/* Bit width of the sample. |
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* Supported values: 16, 24 |
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*/ |
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u16 data_format; |
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/* Data format supported by the SLIMbus hardware. The default is |
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* 0 (#AFE_SB_DATA_FORMAT_NOT_INDICATED), which indicates the |
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* hardware does not perform any format conversions before the data |
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* transfer. |
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*/ |
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u16 num_channels; |
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/* Number of channels. |
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* Supported values: 1 to #AFE_PORT_MAX_AUDIO_CHAN_CNT |
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*/ |
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u8 shared_ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT]; |
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/* Mapping of shared channel IDs (128 to 255) to which the |
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* master port is to be connected. |
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* Shared_channel_mapping[i] represents the shared channel assigned |
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* for audio channel i in multichannel audio data. |
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*/ |
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u32 sample_rate; |
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/* Sampling rate of the port. |
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* Supported values: |
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* - #AFE_PORT_SAMPLE_RATE_8K |
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* - #AFE_PORT_SAMPLE_RATE_16K |
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* - #AFE_PORT_SAMPLE_RATE_48K |
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* - #AFE_PORT_SAMPLE_RATE_96K |
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* - #AFE_PORT_SAMPLE_RATE_192K |
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*/ |
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} __packed; |
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struct afe_clk_cfg { |
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u32 i2s_cfg_minor_version; |
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u32 clk_val1; |
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u32 clk_val2; |
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u16 clk_src; |
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u16 clk_root; |
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u16 clk_set_mode; |
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u16 reserved; |
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} __packed; |
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struct afe_digital_clk_cfg { |
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u32 i2s_cfg_minor_version; |
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u32 clk_val; |
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u16 clk_root; |
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u16 reserved; |
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} __packed; |
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struct afe_param_id_i2s_cfg { |
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u32 i2s_cfg_minor_version; |
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u16 bit_width; |
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u16 channel_mode; |
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u16 mono_stereo; |
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u16 ws_src; |
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u32 sample_rate; |
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u16 data_format; |
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u16 reserved; |
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} __packed; |
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struct afe_param_id_tdm_cfg { |
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u32 tdm_cfg_minor_version; |
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u32 num_channels; |
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u32 sample_rate; |
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u32 bit_width; |
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u16 data_format; |
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u16 sync_mode; |
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u16 sync_src; |
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u16 nslots_per_frame; |
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u16 ctrl_data_out_enable; |
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u16 ctrl_invert_sync_pulse; |
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u16 ctrl_sync_data_delay; |
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u16 slot_width; |
|
u32 slot_mask; |
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} __packed; |
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|
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struct afe_param_id_cdc_dma_cfg { |
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u32 cdc_dma_cfg_minor_version; |
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u32 sample_rate; |
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u16 bit_width; |
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u16 data_format; |
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u16 num_channels; |
|
u16 active_channels_mask; |
|
} __packed; |
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|
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union afe_port_config { |
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struct afe_param_id_hdmi_multi_chan_audio_cfg hdmi_multi_ch; |
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struct afe_param_id_slimbus_cfg slim_cfg; |
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struct afe_param_id_i2s_cfg i2s_cfg; |
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struct afe_param_id_tdm_cfg tdm_cfg; |
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struct afe_param_id_cdc_dma_cfg dma_cfg; |
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} __packed; |
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struct afe_clk_set { |
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uint32_t clk_set_minor_version; |
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uint32_t clk_id; |
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uint32_t clk_freq_in_hz; |
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uint16_t clk_attri; |
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uint16_t clk_root; |
|
uint32_t enable; |
|
}; |
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struct afe_param_id_slot_mapping_cfg { |
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u32 minor_version; |
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u16 num_channels; |
|
u16 bitwidth; |
|
u32 data_align_type; |
|
u16 ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT]; |
|
} __packed; |
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|
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struct q6afe_port { |
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wait_queue_head_t wait; |
|
union afe_port_config port_cfg; |
|
struct afe_param_id_slot_mapping_cfg *scfg; |
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struct aprv2_ibasic_rsp_result_t result; |
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int token; |
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int id; |
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int cfg_type; |
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struct q6afe *afe; |
|
struct kref refcount; |
|
struct list_head node; |
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}; |
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struct afe_cmd_remote_lpass_core_hw_vote_request { |
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uint32_t hw_block_id; |
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char client_name[8]; |
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} __packed; |
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|
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struct afe_cmd_remote_lpass_core_hw_devote_request { |
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uint32_t hw_block_id; |
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uint32_t client_handle; |
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} __packed; |
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struct afe_port_map { |
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int port_id; |
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int token; |
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int is_rx; |
|
int is_dig_pcm; |
|
}; |
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/* |
|
* Mapping between Virtual Port IDs to DSP AFE Port ID |
|
* On B Family SoCs DSP Port IDs are consistent across multiple SoCs |
|
* on A Family SoCs DSP port IDs are same as virtual Port IDs. |
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*/ |
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|
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static struct afe_port_map port_maps[AFE_PORT_MAX] = { |
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[HDMI_RX] = { AFE_PORT_ID_MULTICHAN_HDMI_RX, HDMI_RX, 1, 1}, |
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[SLIMBUS_0_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX, |
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SLIMBUS_0_RX, 1, 1}, |
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[SLIMBUS_1_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX, |
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SLIMBUS_1_RX, 1, 1}, |
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[SLIMBUS_2_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX, |
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SLIMBUS_2_RX, 1, 1}, |
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[SLIMBUS_3_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX, |
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SLIMBUS_3_RX, 1, 1}, |
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[SLIMBUS_4_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX, |
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SLIMBUS_4_RX, 1, 1}, |
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[SLIMBUS_5_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX, |
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SLIMBUS_5_RX, 1, 1}, |
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[SLIMBUS_6_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX, |
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SLIMBUS_6_RX, 1, 1}, |
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[SLIMBUS_0_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX, |
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SLIMBUS_0_TX, 0, 1}, |
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[SLIMBUS_1_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX, |
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SLIMBUS_1_TX, 0, 1}, |
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[SLIMBUS_2_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX, |
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SLIMBUS_2_TX, 0, 1}, |
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[SLIMBUS_3_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX, |
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SLIMBUS_3_TX, 0, 1}, |
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[SLIMBUS_4_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX, |
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SLIMBUS_4_TX, 0, 1}, |
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[SLIMBUS_5_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX, |
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SLIMBUS_5_TX, 0, 1}, |
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[SLIMBUS_6_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX, |
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SLIMBUS_6_TX, 0, 1}, |
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[PRIMARY_MI2S_RX] = { AFE_PORT_ID_PRIMARY_MI2S_RX, |
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PRIMARY_MI2S_RX, 1, 1}, |
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[PRIMARY_MI2S_TX] = { AFE_PORT_ID_PRIMARY_MI2S_TX, |
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PRIMARY_MI2S_RX, 0, 1}, |
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[SECONDARY_MI2S_RX] = { AFE_PORT_ID_SECONDARY_MI2S_RX, |
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SECONDARY_MI2S_RX, 1, 1}, |
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[SECONDARY_MI2S_TX] = { AFE_PORT_ID_SECONDARY_MI2S_TX, |
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SECONDARY_MI2S_TX, 0, 1}, |
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[TERTIARY_MI2S_RX] = { AFE_PORT_ID_TERTIARY_MI2S_RX, |
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TERTIARY_MI2S_RX, 1, 1}, |
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[TERTIARY_MI2S_TX] = { AFE_PORT_ID_TERTIARY_MI2S_TX, |
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TERTIARY_MI2S_TX, 0, 1}, |
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[QUATERNARY_MI2S_RX] = { AFE_PORT_ID_QUATERNARY_MI2S_RX, |
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QUATERNARY_MI2S_RX, 1, 1}, |
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[QUATERNARY_MI2S_TX] = { AFE_PORT_ID_QUATERNARY_MI2S_TX, |
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QUATERNARY_MI2S_TX, 0, 1}, |
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[QUINARY_MI2S_RX] = { AFE_PORT_ID_QUINARY_MI2S_RX, |
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QUINARY_MI2S_RX, 1, 1}, |
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[QUINARY_MI2S_TX] = { AFE_PORT_ID_QUINARY_MI2S_TX, |
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QUINARY_MI2S_TX, 0, 1}, |
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[PRIMARY_TDM_RX_0] = { AFE_PORT_ID_PRIMARY_TDM_RX, |
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PRIMARY_TDM_RX_0, 1, 1}, |
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[PRIMARY_TDM_TX_0] = { AFE_PORT_ID_PRIMARY_TDM_TX, |
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PRIMARY_TDM_TX_0, 0, 1}, |
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[PRIMARY_TDM_RX_1] = { AFE_PORT_ID_PRIMARY_TDM_RX_1, |
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PRIMARY_TDM_RX_1, 1, 1}, |
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[PRIMARY_TDM_TX_1] = { AFE_PORT_ID_PRIMARY_TDM_TX_1, |
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PRIMARY_TDM_TX_1, 0, 1}, |
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[PRIMARY_TDM_RX_2] = { AFE_PORT_ID_PRIMARY_TDM_RX_2, |
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PRIMARY_TDM_RX_2, 1, 1}, |
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[PRIMARY_TDM_TX_2] = { AFE_PORT_ID_PRIMARY_TDM_TX_2, |
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PRIMARY_TDM_TX_2, 0, 1}, |
|
[PRIMARY_TDM_RX_3] = { AFE_PORT_ID_PRIMARY_TDM_RX_3, |
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PRIMARY_TDM_RX_3, 1, 1}, |
|
[PRIMARY_TDM_TX_3] = { AFE_PORT_ID_PRIMARY_TDM_TX_3, |
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PRIMARY_TDM_TX_3, 0, 1}, |
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[PRIMARY_TDM_RX_4] = { AFE_PORT_ID_PRIMARY_TDM_RX_4, |
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PRIMARY_TDM_RX_4, 1, 1}, |
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[PRIMARY_TDM_TX_4] = { AFE_PORT_ID_PRIMARY_TDM_TX_4, |
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PRIMARY_TDM_TX_4, 0, 1}, |
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[PRIMARY_TDM_RX_5] = { AFE_PORT_ID_PRIMARY_TDM_RX_5, |
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PRIMARY_TDM_RX_5, 1, 1}, |
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[PRIMARY_TDM_TX_5] = { AFE_PORT_ID_PRIMARY_TDM_TX_5, |
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PRIMARY_TDM_TX_5, 0, 1}, |
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[PRIMARY_TDM_RX_6] = { AFE_PORT_ID_PRIMARY_TDM_RX_6, |
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PRIMARY_TDM_RX_6, 1, 1}, |
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[PRIMARY_TDM_TX_6] = { AFE_PORT_ID_PRIMARY_TDM_TX_6, |
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PRIMARY_TDM_TX_6, 0, 1}, |
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[PRIMARY_TDM_RX_7] = { AFE_PORT_ID_PRIMARY_TDM_RX_7, |
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PRIMARY_TDM_RX_7, 1, 1}, |
|
[PRIMARY_TDM_TX_7] = { AFE_PORT_ID_PRIMARY_TDM_TX_7, |
|
PRIMARY_TDM_TX_7, 0, 1}, |
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[SECONDARY_TDM_RX_0] = { AFE_PORT_ID_SECONDARY_TDM_RX, |
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SECONDARY_TDM_RX_0, 1, 1}, |
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[SECONDARY_TDM_TX_0] = { AFE_PORT_ID_SECONDARY_TDM_TX, |
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SECONDARY_TDM_TX_0, 0, 1}, |
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[SECONDARY_TDM_RX_1] = { AFE_PORT_ID_SECONDARY_TDM_RX_1, |
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SECONDARY_TDM_RX_1, 1, 1}, |
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[SECONDARY_TDM_TX_1] = { AFE_PORT_ID_SECONDARY_TDM_TX_1, |
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SECONDARY_TDM_TX_1, 0, 1}, |
|
[SECONDARY_TDM_RX_2] = { AFE_PORT_ID_SECONDARY_TDM_RX_2, |
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SECONDARY_TDM_RX_2, 1, 1}, |
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[SECONDARY_TDM_TX_2] = { AFE_PORT_ID_SECONDARY_TDM_TX_2, |
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SECONDARY_TDM_TX_2, 0, 1}, |
|
[SECONDARY_TDM_RX_3] = { AFE_PORT_ID_SECONDARY_TDM_RX_3, |
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SECONDARY_TDM_RX_3, 1, 1}, |
|
[SECONDARY_TDM_TX_3] = { AFE_PORT_ID_SECONDARY_TDM_TX_3, |
|
SECONDARY_TDM_TX_3, 0, 1}, |
|
[SECONDARY_TDM_RX_4] = { AFE_PORT_ID_SECONDARY_TDM_RX_4, |
|
SECONDARY_TDM_RX_4, 1, 1}, |
|
[SECONDARY_TDM_TX_4] = { AFE_PORT_ID_SECONDARY_TDM_TX_4, |
|
SECONDARY_TDM_TX_4, 0, 1}, |
|
[SECONDARY_TDM_RX_5] = { AFE_PORT_ID_SECONDARY_TDM_RX_5, |
|
SECONDARY_TDM_RX_5, 1, 1}, |
|
[SECONDARY_TDM_TX_5] = { AFE_PORT_ID_SECONDARY_TDM_TX_5, |
|
SECONDARY_TDM_TX_5, 0, 1}, |
|
[SECONDARY_TDM_RX_6] = { AFE_PORT_ID_SECONDARY_TDM_RX_6, |
|
SECONDARY_TDM_RX_6, 1, 1}, |
|
[SECONDARY_TDM_TX_6] = { AFE_PORT_ID_SECONDARY_TDM_TX_6, |
|
SECONDARY_TDM_TX_6, 0, 1}, |
|
[SECONDARY_TDM_RX_7] = { AFE_PORT_ID_SECONDARY_TDM_RX_7, |
|
SECONDARY_TDM_RX_7, 1, 1}, |
|
[SECONDARY_TDM_TX_7] = { AFE_PORT_ID_SECONDARY_TDM_TX_7, |
|
SECONDARY_TDM_TX_7, 0, 1}, |
|
[TERTIARY_TDM_RX_0] = { AFE_PORT_ID_TERTIARY_TDM_RX, |
|
TERTIARY_TDM_RX_0, 1, 1}, |
|
[TERTIARY_TDM_TX_0] = { AFE_PORT_ID_TERTIARY_TDM_TX, |
|
TERTIARY_TDM_TX_0, 0, 1}, |
|
[TERTIARY_TDM_RX_1] = { AFE_PORT_ID_TERTIARY_TDM_RX_1, |
|
TERTIARY_TDM_RX_1, 1, 1}, |
|
[TERTIARY_TDM_TX_1] = { AFE_PORT_ID_TERTIARY_TDM_TX_1, |
|
TERTIARY_TDM_TX_1, 0, 1}, |
|
[TERTIARY_TDM_RX_2] = { AFE_PORT_ID_TERTIARY_TDM_RX_2, |
|
TERTIARY_TDM_RX_2, 1, 1}, |
|
[TERTIARY_TDM_TX_2] = { AFE_PORT_ID_TERTIARY_TDM_TX_2, |
|
TERTIARY_TDM_TX_2, 0, 1}, |
|
[TERTIARY_TDM_RX_3] = { AFE_PORT_ID_TERTIARY_TDM_RX_3, |
|
TERTIARY_TDM_RX_3, 1, 1}, |
|
[TERTIARY_TDM_TX_3] = { AFE_PORT_ID_TERTIARY_TDM_TX_3, |
|
TERTIARY_TDM_TX_3, 0, 1}, |
|
[TERTIARY_TDM_RX_4] = { AFE_PORT_ID_TERTIARY_TDM_RX_4, |
|
TERTIARY_TDM_RX_4, 1, 1}, |
|
[TERTIARY_TDM_TX_4] = { AFE_PORT_ID_TERTIARY_TDM_TX_4, |
|
TERTIARY_TDM_TX_4, 0, 1}, |
|
[TERTIARY_TDM_RX_5] = { AFE_PORT_ID_TERTIARY_TDM_RX_5, |
|
TERTIARY_TDM_RX_5, 1, 1}, |
|
[TERTIARY_TDM_TX_5] = { AFE_PORT_ID_TERTIARY_TDM_TX_5, |
|
TERTIARY_TDM_TX_5, 0, 1}, |
|
[TERTIARY_TDM_RX_6] = { AFE_PORT_ID_TERTIARY_TDM_RX_6, |
|
TERTIARY_TDM_RX_6, 1, 1}, |
|
[TERTIARY_TDM_TX_6] = { AFE_PORT_ID_TERTIARY_TDM_TX_6, |
|
TERTIARY_TDM_TX_6, 0, 1}, |
|
[TERTIARY_TDM_RX_7] = { AFE_PORT_ID_TERTIARY_TDM_RX_7, |
|
TERTIARY_TDM_RX_7, 1, 1}, |
|
[TERTIARY_TDM_TX_7] = { AFE_PORT_ID_TERTIARY_TDM_TX_7, |
|
TERTIARY_TDM_TX_7, 0, 1}, |
|
[QUATERNARY_TDM_RX_0] = { AFE_PORT_ID_QUATERNARY_TDM_RX, |
|
QUATERNARY_TDM_RX_0, 1, 1}, |
|
[QUATERNARY_TDM_TX_0] = { AFE_PORT_ID_QUATERNARY_TDM_TX, |
|
QUATERNARY_TDM_TX_0, 0, 1}, |
|
[QUATERNARY_TDM_RX_1] = { AFE_PORT_ID_QUATERNARY_TDM_RX_1, |
|
QUATERNARY_TDM_RX_1, 1, 1}, |
|
[QUATERNARY_TDM_TX_1] = { AFE_PORT_ID_QUATERNARY_TDM_TX_1, |
|
QUATERNARY_TDM_TX_1, 0, 1}, |
|
[QUATERNARY_TDM_RX_2] = { AFE_PORT_ID_QUATERNARY_TDM_RX_2, |
|
QUATERNARY_TDM_RX_2, 1, 1}, |
|
[QUATERNARY_TDM_TX_2] = { AFE_PORT_ID_QUATERNARY_TDM_TX_2, |
|
QUATERNARY_TDM_TX_2, 0, 1}, |
|
[QUATERNARY_TDM_RX_3] = { AFE_PORT_ID_QUATERNARY_TDM_RX_3, |
|
QUATERNARY_TDM_RX_3, 1, 1}, |
|
[QUATERNARY_TDM_TX_3] = { AFE_PORT_ID_QUATERNARY_TDM_TX_3, |
|
QUATERNARY_TDM_TX_3, 0, 1}, |
|
[QUATERNARY_TDM_RX_4] = { AFE_PORT_ID_QUATERNARY_TDM_RX_4, |
|
QUATERNARY_TDM_RX_4, 1, 1}, |
|
[QUATERNARY_TDM_TX_4] = { AFE_PORT_ID_QUATERNARY_TDM_TX_4, |
|
QUATERNARY_TDM_TX_4, 0, 1}, |
|
[QUATERNARY_TDM_RX_5] = { AFE_PORT_ID_QUATERNARY_TDM_RX_5, |
|
QUATERNARY_TDM_RX_5, 1, 1}, |
|
[QUATERNARY_TDM_TX_5] = { AFE_PORT_ID_QUATERNARY_TDM_TX_5, |
|
QUATERNARY_TDM_TX_5, 0, 1}, |
|
[QUATERNARY_TDM_RX_6] = { AFE_PORT_ID_QUATERNARY_TDM_RX_6, |
|
QUATERNARY_TDM_RX_6, 1, 1}, |
|
[QUATERNARY_TDM_TX_6] = { AFE_PORT_ID_QUATERNARY_TDM_TX_6, |
|
QUATERNARY_TDM_TX_6, 0, 1}, |
|
[QUATERNARY_TDM_RX_7] = { AFE_PORT_ID_QUATERNARY_TDM_RX_7, |
|
QUATERNARY_TDM_RX_7, 1, 1}, |
|
[QUATERNARY_TDM_TX_7] = { AFE_PORT_ID_QUATERNARY_TDM_TX_7, |
|
QUATERNARY_TDM_TX_7, 0, 1}, |
|
[QUINARY_TDM_RX_0] = { AFE_PORT_ID_QUINARY_TDM_RX, |
|
QUINARY_TDM_RX_0, 1, 1}, |
|
[QUINARY_TDM_TX_0] = { AFE_PORT_ID_QUINARY_TDM_TX, |
|
QUINARY_TDM_TX_0, 0, 1}, |
|
[QUINARY_TDM_RX_1] = { AFE_PORT_ID_QUINARY_TDM_RX_1, |
|
QUINARY_TDM_RX_1, 1, 1}, |
|
[QUINARY_TDM_TX_1] = { AFE_PORT_ID_QUINARY_TDM_TX_1, |
|
QUINARY_TDM_TX_1, 0, 1}, |
|
[QUINARY_TDM_RX_2] = { AFE_PORT_ID_QUINARY_TDM_RX_2, |
|
QUINARY_TDM_RX_2, 1, 1}, |
|
[QUINARY_TDM_TX_2] = { AFE_PORT_ID_QUINARY_TDM_TX_2, |
|
QUINARY_TDM_TX_2, 0, 1}, |
|
[QUINARY_TDM_RX_3] = { AFE_PORT_ID_QUINARY_TDM_RX_3, |
|
QUINARY_TDM_RX_3, 1, 1}, |
|
[QUINARY_TDM_TX_3] = { AFE_PORT_ID_QUINARY_TDM_TX_3, |
|
QUINARY_TDM_TX_3, 0, 1}, |
|
[QUINARY_TDM_RX_4] = { AFE_PORT_ID_QUINARY_TDM_RX_4, |
|
QUINARY_TDM_RX_4, 1, 1}, |
|
[QUINARY_TDM_TX_4] = { AFE_PORT_ID_QUINARY_TDM_TX_4, |
|
QUINARY_TDM_TX_4, 0, 1}, |
|
[QUINARY_TDM_RX_5] = { AFE_PORT_ID_QUINARY_TDM_RX_5, |
|
QUINARY_TDM_RX_5, 1, 1}, |
|
[QUINARY_TDM_TX_5] = { AFE_PORT_ID_QUINARY_TDM_TX_5, |
|
QUINARY_TDM_TX_5, 0, 1}, |
|
[QUINARY_TDM_RX_6] = { AFE_PORT_ID_QUINARY_TDM_RX_6, |
|
QUINARY_TDM_RX_6, 1, 1}, |
|
[QUINARY_TDM_TX_6] = { AFE_PORT_ID_QUINARY_TDM_TX_6, |
|
QUINARY_TDM_TX_6, 0, 1}, |
|
[QUINARY_TDM_RX_7] = { AFE_PORT_ID_QUINARY_TDM_RX_7, |
|
QUINARY_TDM_RX_7, 1, 1}, |
|
[QUINARY_TDM_TX_7] = { AFE_PORT_ID_QUINARY_TDM_TX_7, |
|
QUINARY_TDM_TX_7, 0, 1}, |
|
[DISPLAY_PORT_RX] = { AFE_PORT_ID_HDMI_OVER_DP_RX, |
|
DISPLAY_PORT_RX, 1, 1}, |
|
[WSA_CODEC_DMA_RX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_0, |
|
WSA_CODEC_DMA_RX_0, 1, 1}, |
|
[WSA_CODEC_DMA_TX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_0, |
|
WSA_CODEC_DMA_TX_0, 0, 1}, |
|
[WSA_CODEC_DMA_RX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_1, |
|
WSA_CODEC_DMA_RX_1, 1, 1}, |
|
[WSA_CODEC_DMA_TX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_1, |
|
WSA_CODEC_DMA_TX_1, 0, 1}, |
|
[WSA_CODEC_DMA_TX_2] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_2, |
|
WSA_CODEC_DMA_TX_2, 0, 1}, |
|
[VA_CODEC_DMA_TX_0] = { AFE_PORT_ID_VA_CODEC_DMA_TX_0, |
|
VA_CODEC_DMA_TX_0, 0, 1}, |
|
[VA_CODEC_DMA_TX_1] = { AFE_PORT_ID_VA_CODEC_DMA_TX_1, |
|
VA_CODEC_DMA_TX_1, 0, 1}, |
|
[VA_CODEC_DMA_TX_2] = { AFE_PORT_ID_VA_CODEC_DMA_TX_2, |
|
VA_CODEC_DMA_TX_2, 0, 1}, |
|
[RX_CODEC_DMA_RX_0] = { AFE_PORT_ID_RX_CODEC_DMA_RX_0, |
|
RX_CODEC_DMA_RX_0, 1, 1}, |
|
[TX_CODEC_DMA_TX_0] = { AFE_PORT_ID_TX_CODEC_DMA_TX_0, |
|
TX_CODEC_DMA_TX_0, 0, 1}, |
|
[RX_CODEC_DMA_RX_1] = { AFE_PORT_ID_RX_CODEC_DMA_RX_1, |
|
RX_CODEC_DMA_RX_1, 1, 1}, |
|
[TX_CODEC_DMA_TX_1] = { AFE_PORT_ID_TX_CODEC_DMA_TX_1, |
|
TX_CODEC_DMA_TX_1, 0, 1}, |
|
[RX_CODEC_DMA_RX_2] = { AFE_PORT_ID_RX_CODEC_DMA_RX_2, |
|
RX_CODEC_DMA_RX_2, 1, 1}, |
|
[TX_CODEC_DMA_TX_2] = { AFE_PORT_ID_TX_CODEC_DMA_TX_2, |
|
TX_CODEC_DMA_TX_2, 0, 1}, |
|
[RX_CODEC_DMA_RX_3] = { AFE_PORT_ID_RX_CODEC_DMA_RX_3, |
|
RX_CODEC_DMA_RX_3, 1, 1}, |
|
[TX_CODEC_DMA_TX_3] = { AFE_PORT_ID_TX_CODEC_DMA_TX_3, |
|
TX_CODEC_DMA_TX_3, 0, 1}, |
|
[RX_CODEC_DMA_RX_4] = { AFE_PORT_ID_RX_CODEC_DMA_RX_4, |
|
RX_CODEC_DMA_RX_4, 1, 1}, |
|
[TX_CODEC_DMA_TX_4] = { AFE_PORT_ID_TX_CODEC_DMA_TX_4, |
|
TX_CODEC_DMA_TX_4, 0, 1}, |
|
[RX_CODEC_DMA_RX_5] = { AFE_PORT_ID_RX_CODEC_DMA_RX_5, |
|
RX_CODEC_DMA_RX_5, 1, 1}, |
|
[TX_CODEC_DMA_TX_5] = { AFE_PORT_ID_TX_CODEC_DMA_TX_5, |
|
TX_CODEC_DMA_TX_5, 0, 1}, |
|
[RX_CODEC_DMA_RX_6] = { AFE_PORT_ID_RX_CODEC_DMA_RX_6, |
|
RX_CODEC_DMA_RX_6, 1, 1}, |
|
[RX_CODEC_DMA_RX_7] = { AFE_PORT_ID_RX_CODEC_DMA_RX_7, |
|
RX_CODEC_DMA_RX_7, 1, 1}, |
|
}; |
|
|
|
static void q6afe_port_free(struct kref *ref) |
|
{ |
|
struct q6afe_port *port; |
|
struct q6afe *afe; |
|
unsigned long flags; |
|
|
|
port = container_of(ref, struct q6afe_port, refcount); |
|
afe = port->afe; |
|
spin_lock_irqsave(&afe->port_list_lock, flags); |
|
list_del(&port->node); |
|
spin_unlock_irqrestore(&afe->port_list_lock, flags); |
|
kfree(port->scfg); |
|
kfree(port); |
|
} |
|
|
|
static struct q6afe_port *q6afe_find_port(struct q6afe *afe, int token) |
|
{ |
|
struct q6afe_port *p; |
|
struct q6afe_port *ret = NULL; |
|
unsigned long flags; |
|
|
|
spin_lock_irqsave(&afe->port_list_lock, flags); |
|
list_for_each_entry(p, &afe->port_list, node) |
|
if (p->token == token) { |
|
ret = p; |
|
kref_get(&p->refcount); |
|
break; |
|
} |
|
|
|
spin_unlock_irqrestore(&afe->port_list_lock, flags); |
|
return ret; |
|
} |
|
|
|
static int q6afe_callback(struct apr_device *adev, struct apr_resp_pkt *data) |
|
{ |
|
struct q6afe *afe = dev_get_drvdata(&adev->dev); |
|
struct aprv2_ibasic_rsp_result_t *res; |
|
struct apr_hdr *hdr = &data->hdr; |
|
struct q6afe_port *port; |
|
|
|
if (!data->payload_size) |
|
return 0; |
|
|
|
res = data->payload; |
|
switch (hdr->opcode) { |
|
case APR_BASIC_RSP_RESULT: { |
|
if (res->status) { |
|
dev_err(afe->dev, "cmd = 0x%x returned error = 0x%x\n", |
|
res->opcode, res->status); |
|
} |
|
switch (res->opcode) { |
|
case AFE_PORT_CMD_SET_PARAM_V2: |
|
case AFE_PORT_CMD_DEVICE_STOP: |
|
case AFE_PORT_CMD_DEVICE_START: |
|
case AFE_SVC_CMD_SET_PARAM: |
|
port = q6afe_find_port(afe, hdr->token); |
|
if (port) { |
|
port->result = *res; |
|
wake_up(&port->wait); |
|
kref_put(&port->refcount, q6afe_port_free); |
|
} else if (hdr->token == AFE_CLK_TOKEN) { |
|
afe->result = *res; |
|
wake_up(&afe->wait); |
|
} |
|
break; |
|
default: |
|
dev_err(afe->dev, "Unknown cmd 0x%x\n", res->opcode); |
|
break; |
|
} |
|
} |
|
break; |
|
case AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST: |
|
afe->result.opcode = hdr->opcode; |
|
afe->result.status = res->status; |
|
wake_up(&afe->wait); |
|
break; |
|
default: |
|
break; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* q6afe_get_port_id() - Get port id from a given port index |
|
* |
|
* @index: port index |
|
* |
|
* Return: Will be an negative on error or valid port_id on success |
|
*/ |
|
int q6afe_get_port_id(int index) |
|
{ |
|
if (index < 0 || index >= AFE_PORT_MAX) |
|
return -EINVAL; |
|
|
|
return port_maps[index].port_id; |
|
} |
|
EXPORT_SYMBOL_GPL(q6afe_get_port_id); |
|
|
|
static int afe_apr_send_pkt(struct q6afe *afe, struct apr_pkt *pkt, |
|
struct q6afe_port *port, uint32_t rsp_opcode) |
|
{ |
|
wait_queue_head_t *wait; |
|
struct aprv2_ibasic_rsp_result_t *result; |
|
int ret; |
|
|
|
mutex_lock(&afe->lock); |
|
if (port) { |
|
wait = &port->wait; |
|
result = &port->result; |
|
} else { |
|
result = &afe->result; |
|
wait = &afe->wait; |
|
} |
|
|
|
result->opcode = 0; |
|
result->status = 0; |
|
|
|
ret = apr_send_pkt(afe->apr, pkt); |
|
if (ret < 0) { |
|
dev_err(afe->dev, "packet not transmitted (%d)\n", ret); |
|
ret = -EINVAL; |
|
goto err; |
|
} |
|
|
|
ret = wait_event_timeout(*wait, (result->opcode == rsp_opcode), |
|
msecs_to_jiffies(TIMEOUT_MS)); |
|
if (!ret) { |
|
ret = -ETIMEDOUT; |
|
} else if (result->status > 0) { |
|
dev_err(afe->dev, "DSP returned error[%x]\n", |
|
result->status); |
|
ret = -EINVAL; |
|
} else { |
|
ret = 0; |
|
} |
|
|
|
err: |
|
mutex_unlock(&afe->lock); |
|
|
|
return ret; |
|
} |
|
|
|
static int q6afe_set_param(struct q6afe *afe, struct q6afe_port *port, |
|
void *data, int param_id, int module_id, int psize, |
|
int token) |
|
{ |
|
struct afe_svc_cmd_set_param *param; |
|
struct afe_port_param_data_v2 *pdata; |
|
struct apr_pkt *pkt; |
|
int ret, pkt_size; |
|
void *p, *pl; |
|
|
|
pkt_size = APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata) + psize; |
|
p = kzalloc(pkt_size, GFP_KERNEL); |
|
if (!p) |
|
return -ENOMEM; |
|
|
|
pkt = p; |
|
param = p + APR_HDR_SIZE; |
|
pdata = p + APR_HDR_SIZE + sizeof(*param); |
|
pl = p + APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata); |
|
memcpy(pl, data, psize); |
|
|
|
pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, |
|
APR_HDR_LEN(APR_HDR_SIZE), |
|
APR_PKT_VER); |
|
pkt->hdr.pkt_size = pkt_size; |
|
pkt->hdr.src_port = 0; |
|
pkt->hdr.dest_port = 0; |
|
pkt->hdr.token = token; |
|
pkt->hdr.opcode = AFE_SVC_CMD_SET_PARAM; |
|
|
|
param->payload_size = sizeof(*pdata) + psize; |
|
param->payload_address_lsw = 0x00; |
|
param->payload_address_msw = 0x00; |
|
param->mem_map_handle = 0x00; |
|
pdata->module_id = module_id; |
|
pdata->param_id = param_id; |
|
pdata->param_size = psize; |
|
|
|
ret = afe_apr_send_pkt(afe, pkt, port, AFE_SVC_CMD_SET_PARAM); |
|
if (ret) |
|
dev_err(afe->dev, "AFE set params failed %d\n", ret); |
|
|
|
kfree(pkt); |
|
return ret; |
|
} |
|
|
|
static int q6afe_port_set_param(struct q6afe_port *port, void *data, |
|
int param_id, int module_id, int psize) |
|
{ |
|
return q6afe_set_param(port->afe, port, data, param_id, module_id, |
|
psize, port->token); |
|
} |
|
|
|
static int q6afe_port_set_param_v2(struct q6afe_port *port, void *data, |
|
int param_id, int module_id, int psize) |
|
{ |
|
struct afe_port_cmd_set_param_v2 *param; |
|
struct afe_port_param_data_v2 *pdata; |
|
struct q6afe *afe = port->afe; |
|
struct apr_pkt *pkt; |
|
u16 port_id = port->id; |
|
int ret, pkt_size; |
|
void *p, *pl; |
|
|
|
pkt_size = APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata) + psize; |
|
p = kzalloc(pkt_size, GFP_KERNEL); |
|
if (!p) |
|
return -ENOMEM; |
|
|
|
pkt = p; |
|
param = p + APR_HDR_SIZE; |
|
pdata = p + APR_HDR_SIZE + sizeof(*param); |
|
pl = p + APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata); |
|
memcpy(pl, data, psize); |
|
|
|
pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, |
|
APR_HDR_LEN(APR_HDR_SIZE), |
|
APR_PKT_VER); |
|
pkt->hdr.pkt_size = pkt_size; |
|
pkt->hdr.src_port = 0; |
|
pkt->hdr.dest_port = 0; |
|
pkt->hdr.token = port->token; |
|
pkt->hdr.opcode = AFE_PORT_CMD_SET_PARAM_V2; |
|
|
|
param->port_id = port_id; |
|
param->payload_size = sizeof(*pdata) + psize; |
|
param->payload_address_lsw = 0x00; |
|
param->payload_address_msw = 0x00; |
|
param->mem_map_handle = 0x00; |
|
pdata->module_id = module_id; |
|
pdata->param_id = param_id; |
|
pdata->param_size = psize; |
|
|
|
ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_SET_PARAM_V2); |
|
if (ret) |
|
dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", |
|
port_id, ret); |
|
|
|
kfree(pkt); |
|
return ret; |
|
} |
|
|
|
static int q6afe_port_set_lpass_clock(struct q6afe_port *port, |
|
struct afe_clk_cfg *cfg) |
|
{ |
|
return q6afe_port_set_param_v2(port, cfg, |
|
AFE_PARAM_ID_LPAIF_CLK_CONFIG, |
|
AFE_MODULE_AUDIO_DEV_INTERFACE, |
|
sizeof(*cfg)); |
|
} |
|
|
|
static int q6afe_set_lpass_clock_v2(struct q6afe_port *port, |
|
struct afe_clk_set *cfg) |
|
{ |
|
return q6afe_port_set_param(port, cfg, AFE_PARAM_ID_CLOCK_SET, |
|
AFE_MODULE_CLOCK_SET, sizeof(*cfg)); |
|
} |
|
|
|
static int q6afe_set_digital_codec_core_clock(struct q6afe_port *port, |
|
struct afe_digital_clk_cfg *cfg) |
|
{ |
|
return q6afe_port_set_param_v2(port, cfg, |
|
AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG, |
|
AFE_MODULE_AUDIO_DEV_INTERFACE, |
|
sizeof(*cfg)); |
|
} |
|
|
|
int q6afe_set_lpass_clock(struct device *dev, int clk_id, int attri, |
|
int clk_root, unsigned int freq) |
|
{ |
|
struct q6afe *afe = dev_get_drvdata(dev->parent); |
|
struct afe_clk_set cset = {0,}; |
|
|
|
cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET; |
|
cset.clk_id = clk_id; |
|
cset.clk_freq_in_hz = freq; |
|
cset.clk_attri = attri; |
|
cset.clk_root = clk_root; |
|
cset.enable = !!freq; |
|
|
|
return q6afe_set_param(afe, NULL, &cset, AFE_PARAM_ID_CLOCK_SET, |
|
AFE_MODULE_CLOCK_SET, sizeof(cset), |
|
AFE_CLK_TOKEN); |
|
} |
|
EXPORT_SYMBOL_GPL(q6afe_set_lpass_clock); |
|
|
|
int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id, |
|
int clk_src, int clk_root, |
|
unsigned int freq, int dir) |
|
{ |
|
struct afe_clk_cfg ccfg = {0,}; |
|
struct afe_clk_set cset = {0,}; |
|
struct afe_digital_clk_cfg dcfg = {0,}; |
|
int ret; |
|
|
|
switch (clk_id) { |
|
case LPAIF_DIG_CLK: |
|
dcfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; |
|
dcfg.clk_val = freq; |
|
dcfg.clk_root = clk_root; |
|
ret = q6afe_set_digital_codec_core_clock(port, &dcfg); |
|
break; |
|
case LPAIF_BIT_CLK: |
|
ccfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; |
|
ccfg.clk_val1 = freq; |
|
ccfg.clk_src = clk_src; |
|
ccfg.clk_root = clk_root; |
|
ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK1_VALID; |
|
ret = q6afe_port_set_lpass_clock(port, &ccfg); |
|
break; |
|
|
|
case LPAIF_OSR_CLK: |
|
ccfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; |
|
ccfg.clk_val2 = freq; |
|
ccfg.clk_src = clk_src; |
|
ccfg.clk_root = clk_root; |
|
ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK2_VALID; |
|
ret = q6afe_port_set_lpass_clock(port, &ccfg); |
|
break; |
|
case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR: |
|
case Q6AFE_LPASS_CLK_ID_MCLK_1 ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1: |
|
case Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT ... Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT: |
|
case Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK ... Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK: |
|
cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET; |
|
cset.clk_id = clk_id; |
|
cset.clk_freq_in_hz = freq; |
|
cset.clk_attri = clk_src; |
|
cset.clk_root = clk_root; |
|
cset.enable = !!freq; |
|
ret = q6afe_set_lpass_clock_v2(port, &cset); |
|
break; |
|
default: |
|
ret = -EINVAL; |
|
break; |
|
} |
|
|
|
return ret; |
|
} |
|
EXPORT_SYMBOL_GPL(q6afe_port_set_sysclk); |
|
|
|
/** |
|
* q6afe_port_stop() - Stop a afe port |
|
* |
|
* @port: Instance of port to stop |
|
* |
|
* Return: Will be an negative on packet size on success. |
|
*/ |
|
int q6afe_port_stop(struct q6afe_port *port) |
|
{ |
|
struct afe_port_cmd_device_stop *stop; |
|
struct q6afe *afe = port->afe; |
|
struct apr_pkt *pkt; |
|
int port_id = port->id; |
|
int ret = 0; |
|
int index, pkt_size; |
|
void *p; |
|
|
|
index = port->token; |
|
if (index < 0 || index >= AFE_PORT_MAX) { |
|
dev_err(afe->dev, "AFE port index[%d] invalid!\n", index); |
|
return -EINVAL; |
|
} |
|
|
|
pkt_size = APR_HDR_SIZE + sizeof(*stop); |
|
p = kzalloc(pkt_size, GFP_KERNEL); |
|
if (!p) |
|
return -ENOMEM; |
|
|
|
pkt = p; |
|
stop = p + APR_HDR_SIZE; |
|
|
|
pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, |
|
APR_HDR_LEN(APR_HDR_SIZE), |
|
APR_PKT_VER); |
|
pkt->hdr.pkt_size = pkt_size; |
|
pkt->hdr.src_port = 0; |
|
pkt->hdr.dest_port = 0; |
|
pkt->hdr.token = index; |
|
pkt->hdr.opcode = AFE_PORT_CMD_DEVICE_STOP; |
|
stop->port_id = port_id; |
|
stop->reserved = 0; |
|
|
|
ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_DEVICE_STOP); |
|
if (ret) |
|
dev_err(afe->dev, "AFE close failed %d\n", ret); |
|
|
|
kfree(pkt); |
|
return ret; |
|
} |
|
EXPORT_SYMBOL_GPL(q6afe_port_stop); |
|
|
|
/** |
|
* q6afe_slim_port_prepare() - Prepare slim afe port. |
|
* |
|
* @port: Instance of afe port |
|
* @cfg: SLIM configuration for the afe port |
|
* |
|
*/ |
|
void q6afe_slim_port_prepare(struct q6afe_port *port, |
|
struct q6afe_slim_cfg *cfg) |
|
{ |
|
union afe_port_config *pcfg = &port->port_cfg; |
|
|
|
pcfg->slim_cfg.sb_cfg_minor_version = AFE_API_VERSION_SLIMBUS_CONFIG; |
|
pcfg->slim_cfg.sample_rate = cfg->sample_rate; |
|
pcfg->slim_cfg.bit_width = cfg->bit_width; |
|
pcfg->slim_cfg.num_channels = cfg->num_channels; |
|
pcfg->slim_cfg.data_format = cfg->data_format; |
|
pcfg->slim_cfg.shared_ch_mapping[0] = cfg->ch_mapping[0]; |
|
pcfg->slim_cfg.shared_ch_mapping[1] = cfg->ch_mapping[1]; |
|
pcfg->slim_cfg.shared_ch_mapping[2] = cfg->ch_mapping[2]; |
|
pcfg->slim_cfg.shared_ch_mapping[3] = cfg->ch_mapping[3]; |
|
|
|
} |
|
EXPORT_SYMBOL_GPL(q6afe_slim_port_prepare); |
|
|
|
/** |
|
* q6afe_tdm_port_prepare() - Prepare tdm afe port. |
|
* |
|
* @port: Instance of afe port |
|
* @cfg: TDM configuration for the afe port |
|
* |
|
*/ |
|
void q6afe_tdm_port_prepare(struct q6afe_port *port, |
|
struct q6afe_tdm_cfg *cfg) |
|
{ |
|
union afe_port_config *pcfg = &port->port_cfg; |
|
|
|
pcfg->tdm_cfg.tdm_cfg_minor_version = AFE_API_VERSION_TDM_CONFIG; |
|
pcfg->tdm_cfg.num_channels = cfg->num_channels; |
|
pcfg->tdm_cfg.sample_rate = cfg->sample_rate; |
|
pcfg->tdm_cfg.bit_width = cfg->bit_width; |
|
pcfg->tdm_cfg.data_format = cfg->data_format; |
|
pcfg->tdm_cfg.sync_mode = cfg->sync_mode; |
|
pcfg->tdm_cfg.sync_src = cfg->sync_src; |
|
pcfg->tdm_cfg.nslots_per_frame = cfg->nslots_per_frame; |
|
|
|
pcfg->tdm_cfg.slot_width = cfg->slot_width; |
|
pcfg->tdm_cfg.slot_mask = cfg->slot_mask; |
|
port->scfg = kzalloc(sizeof(*port->scfg), GFP_KERNEL); |
|
if (!port->scfg) |
|
return; |
|
|
|
port->scfg->minor_version = AFE_API_VERSION_SLOT_MAPPING_CONFIG; |
|
port->scfg->num_channels = cfg->num_channels; |
|
port->scfg->bitwidth = cfg->bit_width; |
|
port->scfg->data_align_type = cfg->data_align_type; |
|
memcpy(port->scfg->ch_mapping, cfg->ch_mapping, |
|
sizeof(u16) * AFE_PORT_MAX_AUDIO_CHAN_CNT); |
|
} |
|
EXPORT_SYMBOL_GPL(q6afe_tdm_port_prepare); |
|
|
|
/** |
|
* q6afe_hdmi_port_prepare() - Prepare hdmi afe port. |
|
* |
|
* @port: Instance of afe port |
|
* @cfg: HDMI configuration for the afe port |
|
* |
|
*/ |
|
void q6afe_hdmi_port_prepare(struct q6afe_port *port, |
|
struct q6afe_hdmi_cfg *cfg) |
|
{ |
|
union afe_port_config *pcfg = &port->port_cfg; |
|
|
|
pcfg->hdmi_multi_ch.hdmi_cfg_minor_version = |
|
AFE_API_VERSION_HDMI_CONFIG; |
|
pcfg->hdmi_multi_ch.datatype = cfg->datatype; |
|
pcfg->hdmi_multi_ch.channel_allocation = cfg->channel_allocation; |
|
pcfg->hdmi_multi_ch.sample_rate = cfg->sample_rate; |
|
pcfg->hdmi_multi_ch.bit_width = cfg->bit_width; |
|
} |
|
EXPORT_SYMBOL_GPL(q6afe_hdmi_port_prepare); |
|
|
|
/** |
|
* q6afe_i2s_port_prepare() - Prepare i2s afe port. |
|
* |
|
* @port: Instance of afe port |
|
* @cfg: I2S configuration for the afe port |
|
* Return: Will be an negative on error and zero on success. |
|
*/ |
|
int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg) |
|
{ |
|
union afe_port_config *pcfg = &port->port_cfg; |
|
struct device *dev = port->afe->dev; |
|
int num_sd_lines; |
|
|
|
pcfg->i2s_cfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; |
|
pcfg->i2s_cfg.sample_rate = cfg->sample_rate; |
|
pcfg->i2s_cfg.bit_width = cfg->bit_width; |
|
pcfg->i2s_cfg.data_format = AFE_LINEAR_PCM_DATA; |
|
|
|
switch (cfg->fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
|
case SND_SOC_DAIFMT_CBS_CFS: |
|
pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL; |
|
break; |
|
case SND_SOC_DAIFMT_CBM_CFM: |
|
/* CPU is slave */ |
|
pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL; |
|
break; |
|
default: |
|
break; |
|
} |
|
|
|
num_sd_lines = hweight_long(cfg->sd_line_mask); |
|
|
|
switch (num_sd_lines) { |
|
case 0: |
|
dev_err(dev, "no line is assigned\n"); |
|
return -EINVAL; |
|
case 1: |
|
switch (cfg->sd_line_mask) { |
|
case AFE_PORT_I2S_SD0_MASK: |
|
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0; |
|
break; |
|
case AFE_PORT_I2S_SD1_MASK: |
|
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD1; |
|
break; |
|
case AFE_PORT_I2S_SD2_MASK: |
|
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2; |
|
break; |
|
case AFE_PORT_I2S_SD3_MASK: |
|
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD3; |
|
break; |
|
default: |
|
dev_err(dev, "Invalid SD lines\n"); |
|
return -EINVAL; |
|
} |
|
break; |
|
case 2: |
|
switch (cfg->sd_line_mask) { |
|
case AFE_PORT_I2S_SD0_1_MASK: |
|
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD01; |
|
break; |
|
case AFE_PORT_I2S_SD2_3_MASK: |
|
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD23; |
|
break; |
|
default: |
|
dev_err(dev, "Invalid SD lines\n"); |
|
return -EINVAL; |
|
} |
|
break; |
|
case 3: |
|
switch (cfg->sd_line_mask) { |
|
case AFE_PORT_I2S_SD0_1_2_MASK: |
|
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_6CHS; |
|
break; |
|
default: |
|
dev_err(dev, "Invalid SD lines\n"); |
|
return -EINVAL; |
|
} |
|
break; |
|
case 4: |
|
switch (cfg->sd_line_mask) { |
|
case AFE_PORT_I2S_SD0_1_2_3_MASK: |
|
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_8CHS; |
|
|
|
break; |
|
default: |
|
dev_err(dev, "Invalid SD lines\n"); |
|
return -EINVAL; |
|
} |
|
break; |
|
default: |
|
dev_err(dev, "Invalid SD lines\n"); |
|
return -EINVAL; |
|
} |
|
|
|
switch (cfg->num_channels) { |
|
case 1: |
|
case 2: |
|
switch (pcfg->i2s_cfg.channel_mode) { |
|
case AFE_PORT_I2S_QUAD01: |
|
case AFE_PORT_I2S_6CHS: |
|
case AFE_PORT_I2S_8CHS: |
|
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0; |
|
break; |
|
case AFE_PORT_I2S_QUAD23: |
|
pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2; |
|
break; |
|
} |
|
|
|
if (cfg->num_channels == 2) |
|
pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_STEREO; |
|
else |
|
pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_MONO; |
|
|
|
break; |
|
case 3: |
|
case 4: |
|
if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_QUAD01) { |
|
dev_err(dev, "Invalid Channel mode\n"); |
|
return -EINVAL; |
|
} |
|
break; |
|
case 5: |
|
case 6: |
|
if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_6CHS) { |
|
dev_err(dev, "Invalid Channel mode\n"); |
|
return -EINVAL; |
|
} |
|
break; |
|
case 7: |
|
case 8: |
|
if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_8CHS) { |
|
dev_err(dev, "Invalid Channel mode\n"); |
|
return -EINVAL; |
|
} |
|
break; |
|
default: |
|
break; |
|
} |
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(q6afe_i2s_port_prepare); |
|
|
|
/** |
|
* q6afe_cdc_dma_port_prepare() - Prepare dma afe port. |
|
* |
|
* @port: Instance of afe port |
|
* @cfg: DMA configuration for the afe port |
|
* |
|
*/ |
|
void q6afe_cdc_dma_port_prepare(struct q6afe_port *port, |
|
struct q6afe_cdc_dma_cfg *cfg) |
|
{ |
|
union afe_port_config *pcfg = &port->port_cfg; |
|
struct afe_param_id_cdc_dma_cfg *dma_cfg = &pcfg->dma_cfg; |
|
|
|
dma_cfg->cdc_dma_cfg_minor_version = AFE_API_VERSION_CODEC_DMA_CONFIG; |
|
dma_cfg->sample_rate = cfg->sample_rate; |
|
dma_cfg->bit_width = cfg->bit_width; |
|
dma_cfg->data_format = cfg->data_format; |
|
dma_cfg->num_channels = cfg->num_channels; |
|
if (!cfg->active_channels_mask) |
|
dma_cfg->active_channels_mask = (1 << cfg->num_channels) - 1; |
|
} |
|
EXPORT_SYMBOL_GPL(q6afe_cdc_dma_port_prepare); |
|
/** |
|
* q6afe_port_start() - Start a afe port |
|
* |
|
* @port: Instance of port to start |
|
* |
|
* Return: Will be an negative on packet size on success. |
|
*/ |
|
int q6afe_port_start(struct q6afe_port *port) |
|
{ |
|
struct afe_port_cmd_device_start *start; |
|
struct q6afe *afe = port->afe; |
|
int port_id = port->id; |
|
int ret, param_id = port->cfg_type; |
|
struct apr_pkt *pkt; |
|
int pkt_size; |
|
void *p; |
|
|
|
ret = q6afe_port_set_param_v2(port, &port->port_cfg, param_id, |
|
AFE_MODULE_AUDIO_DEV_INTERFACE, |
|
sizeof(port->port_cfg)); |
|
if (ret) { |
|
dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", |
|
port_id, ret); |
|
return ret; |
|
} |
|
|
|
if (port->scfg) { |
|
ret = q6afe_port_set_param_v2(port, port->scfg, |
|
AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG, |
|
AFE_MODULE_TDM, sizeof(*port->scfg)); |
|
if (ret) { |
|
dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", |
|
port_id, ret); |
|
return ret; |
|
} |
|
} |
|
|
|
pkt_size = APR_HDR_SIZE + sizeof(*start); |
|
p = kzalloc(pkt_size, GFP_KERNEL); |
|
if (!p) |
|
return -ENOMEM; |
|
|
|
pkt = p; |
|
start = p + APR_HDR_SIZE; |
|
|
|
pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, |
|
APR_HDR_LEN(APR_HDR_SIZE), |
|
APR_PKT_VER); |
|
pkt->hdr.pkt_size = pkt_size; |
|
pkt->hdr.src_port = 0; |
|
pkt->hdr.dest_port = 0; |
|
pkt->hdr.token = port->token; |
|
pkt->hdr.opcode = AFE_PORT_CMD_DEVICE_START; |
|
|
|
start->port_id = port_id; |
|
|
|
ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_DEVICE_START); |
|
if (ret) |
|
dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", |
|
port_id, ret); |
|
|
|
kfree(pkt); |
|
return ret; |
|
} |
|
EXPORT_SYMBOL_GPL(q6afe_port_start); |
|
|
|
/** |
|
* q6afe_port_get_from_id() - Get port instance from a port id |
|
* |
|
* @dev: Pointer to afe child device. |
|
* @id: port id |
|
* |
|
* Return: Will be an error pointer on error or a valid afe port |
|
* on success. |
|
*/ |
|
struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id) |
|
{ |
|
int port_id; |
|
struct q6afe *afe = dev_get_drvdata(dev->parent); |
|
struct q6afe_port *port; |
|
unsigned long flags; |
|
int cfg_type; |
|
|
|
if (id < 0 || id >= AFE_PORT_MAX) { |
|
dev_err(dev, "AFE port token[%d] invalid!\n", id); |
|
return ERR_PTR(-EINVAL); |
|
} |
|
|
|
/* if port is multiple times bind/unbind before callback finishes */ |
|
port = q6afe_find_port(afe, id); |
|
if (port) { |
|
dev_err(dev, "AFE Port already open\n"); |
|
return port; |
|
} |
|
|
|
port_id = port_maps[id].port_id; |
|
|
|
switch (port_id) { |
|
case AFE_PORT_ID_MULTICHAN_HDMI_RX: |
|
case AFE_PORT_ID_HDMI_OVER_DP_RX: |
|
cfg_type = AFE_PARAM_ID_HDMI_CONFIG; |
|
break; |
|
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX: |
|
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX: |
|
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX: |
|
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX: |
|
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX: |
|
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX: |
|
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX: |
|
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX: |
|
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX: |
|
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX: |
|
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX: |
|
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX: |
|
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX: |
|
case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX: |
|
cfg_type = AFE_PARAM_ID_SLIMBUS_CONFIG; |
|
break; |
|
|
|
case AFE_PORT_ID_PRIMARY_MI2S_RX: |
|
case AFE_PORT_ID_PRIMARY_MI2S_TX: |
|
case AFE_PORT_ID_SECONDARY_MI2S_RX: |
|
case AFE_PORT_ID_SECONDARY_MI2S_TX: |
|
case AFE_PORT_ID_TERTIARY_MI2S_RX: |
|
case AFE_PORT_ID_TERTIARY_MI2S_TX: |
|
case AFE_PORT_ID_QUATERNARY_MI2S_RX: |
|
case AFE_PORT_ID_QUATERNARY_MI2S_TX: |
|
case AFE_PORT_ID_QUINARY_MI2S_RX: |
|
case AFE_PORT_ID_QUINARY_MI2S_TX: |
|
cfg_type = AFE_PARAM_ID_I2S_CONFIG; |
|
break; |
|
case AFE_PORT_ID_PRIMARY_TDM_RX ... AFE_PORT_ID_QUINARY_TDM_TX_7: |
|
cfg_type = AFE_PARAM_ID_TDM_CONFIG; |
|
break; |
|
case AFE_PORT_ID_WSA_CODEC_DMA_RX_0 ... AFE_PORT_ID_RX_CODEC_DMA_RX_7: |
|
cfg_type = AFE_PARAM_ID_CODEC_DMA_CONFIG; |
|
break; |
|
default: |
|
dev_err(dev, "Invalid port id 0x%x\n", port_id); |
|
return ERR_PTR(-EINVAL); |
|
} |
|
|
|
port = kzalloc(sizeof(*port), GFP_KERNEL); |
|
if (!port) |
|
return ERR_PTR(-ENOMEM); |
|
|
|
init_waitqueue_head(&port->wait); |
|
|
|
port->token = id; |
|
port->id = port_id; |
|
port->afe = afe; |
|
port->cfg_type = cfg_type; |
|
kref_init(&port->refcount); |
|
|
|
spin_lock_irqsave(&afe->port_list_lock, flags); |
|
list_add_tail(&port->node, &afe->port_list); |
|
spin_unlock_irqrestore(&afe->port_list_lock, flags); |
|
|
|
return port; |
|
|
|
} |
|
EXPORT_SYMBOL_GPL(q6afe_port_get_from_id); |
|
|
|
/** |
|
* q6afe_port_put() - Release port reference |
|
* |
|
* @port: Instance of port to put |
|
*/ |
|
void q6afe_port_put(struct q6afe_port *port) |
|
{ |
|
kref_put(&port->refcount, q6afe_port_free); |
|
} |
|
EXPORT_SYMBOL_GPL(q6afe_port_put); |
|
|
|
int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, |
|
uint32_t client_handle) |
|
{ |
|
struct q6afe *afe = dev_get_drvdata(dev->parent); |
|
struct afe_cmd_remote_lpass_core_hw_devote_request *vote_cfg; |
|
struct apr_pkt *pkt; |
|
int ret = 0; |
|
int pkt_size; |
|
void *p; |
|
|
|
pkt_size = APR_HDR_SIZE + sizeof(*vote_cfg); |
|
p = kzalloc(pkt_size, GFP_KERNEL); |
|
if (!p) |
|
return -ENOMEM; |
|
|
|
pkt = p; |
|
vote_cfg = p + APR_HDR_SIZE; |
|
|
|
pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, |
|
APR_HDR_LEN(APR_HDR_SIZE), |
|
APR_PKT_VER); |
|
pkt->hdr.pkt_size = pkt_size; |
|
pkt->hdr.src_port = 0; |
|
pkt->hdr.dest_port = 0; |
|
pkt->hdr.token = hw_block_id; |
|
pkt->hdr.opcode = AFE_CMD_REMOTE_LPASS_CORE_HW_DEVOTE_REQUEST; |
|
vote_cfg->hw_block_id = hw_block_id; |
|
vote_cfg->client_handle = client_handle; |
|
|
|
ret = apr_send_pkt(afe->apr, pkt); |
|
if (ret < 0) |
|
dev_err(afe->dev, "AFE failed to unvote (%d)\n", hw_block_id); |
|
|
|
kfree(pkt); |
|
return ret; |
|
} |
|
EXPORT_SYMBOL(q6afe_unvote_lpass_core_hw); |
|
|
|
int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, |
|
const char *client_name, uint32_t *client_handle) |
|
{ |
|
struct q6afe *afe = dev_get_drvdata(dev->parent); |
|
struct afe_cmd_remote_lpass_core_hw_vote_request *vote_cfg; |
|
struct apr_pkt *pkt; |
|
int ret = 0; |
|
int pkt_size; |
|
void *p; |
|
|
|
pkt_size = APR_HDR_SIZE + sizeof(*vote_cfg); |
|
p = kzalloc(pkt_size, GFP_KERNEL); |
|
if (!p) |
|
return -ENOMEM; |
|
|
|
pkt = p; |
|
vote_cfg = p + APR_HDR_SIZE; |
|
|
|
pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, |
|
APR_HDR_LEN(APR_HDR_SIZE), |
|
APR_PKT_VER); |
|
pkt->hdr.pkt_size = pkt_size; |
|
pkt->hdr.src_port = 0; |
|
pkt->hdr.dest_port = 0; |
|
pkt->hdr.token = hw_block_id; |
|
pkt->hdr.opcode = AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST; |
|
vote_cfg->hw_block_id = hw_block_id; |
|
strscpy(vote_cfg->client_name, client_name, |
|
sizeof(vote_cfg->client_name)); |
|
|
|
ret = afe_apr_send_pkt(afe, pkt, NULL, |
|
AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST); |
|
if (ret) |
|
dev_err(afe->dev, "AFE failed to vote (%d)\n", hw_block_id); |
|
|
|
|
|
kfree(pkt); |
|
return ret; |
|
} |
|
EXPORT_SYMBOL(q6afe_vote_lpass_core_hw); |
|
|
|
static int q6afe_probe(struct apr_device *adev) |
|
{ |
|
struct q6afe *afe; |
|
struct device *dev = &adev->dev; |
|
|
|
afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL); |
|
if (!afe) |
|
return -ENOMEM; |
|
|
|
q6core_get_svc_api_info(adev->svc_id, &afe->ainfo); |
|
afe->apr = adev; |
|
mutex_init(&afe->lock); |
|
init_waitqueue_head(&afe->wait); |
|
afe->dev = dev; |
|
INIT_LIST_HEAD(&afe->port_list); |
|
spin_lock_init(&afe->port_list_lock); |
|
|
|
dev_set_drvdata(dev, afe); |
|
|
|
return devm_of_platform_populate(dev); |
|
} |
|
|
|
#ifdef CONFIG_OF |
|
static const struct of_device_id q6afe_device_id[] = { |
|
{ .compatible = "qcom,q6afe" }, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, q6afe_device_id); |
|
#endif |
|
|
|
static struct apr_driver qcom_q6afe_driver = { |
|
.probe = q6afe_probe, |
|
.callback = q6afe_callback, |
|
.driver = { |
|
.name = "qcom-q6afe", |
|
.of_match_table = of_match_ptr(q6afe_device_id), |
|
|
|
}, |
|
}; |
|
|
|
module_apr_driver(qcom_q6afe_driver); |
|
MODULE_DESCRIPTION("Q6 Audio Front End"); |
|
MODULE_LICENSE("GPL v2");
|
|
|