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554 lines
19 KiB
554 lines
19 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _ASM_IA64_PGTABLE_H |
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#define _ASM_IA64_PGTABLE_H |
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|
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/* |
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* This file contains the functions and defines necessary to modify and use |
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* the IA-64 page table tree. |
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* |
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* This hopefully works with any (fixed) IA-64 page-size, as defined |
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* in <asm/page.h>. |
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* |
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* Copyright (C) 1998-2005 Hewlett-Packard Co |
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* David Mosberger-Tang <[email protected]> |
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*/ |
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#include <asm/mman.h> |
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#include <asm/page.h> |
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#include <asm/processor.h> |
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#include <asm/types.h> |
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#define IA64_MAX_PHYS_BITS 50 /* max. number of physical address bits (architected) */ |
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/* |
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* First, define the various bits in a PTE. Note that the PTE format |
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* matches the VHPT short format, the firt doubleword of the VHPD long |
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* format, and the first doubleword of the TLB insertion format. |
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*/ |
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#define _PAGE_P_BIT 0 |
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#define _PAGE_A_BIT 5 |
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#define _PAGE_D_BIT 6 |
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#define _PAGE_P (1 << _PAGE_P_BIT) /* page present bit */ |
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#define _PAGE_MA_WB (0x0 << 2) /* write back memory attribute */ |
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#define _PAGE_MA_UC (0x4 << 2) /* uncacheable memory attribute */ |
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#define _PAGE_MA_UCE (0x5 << 2) /* UC exported attribute */ |
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#define _PAGE_MA_WC (0x6 << 2) /* write coalescing memory attribute */ |
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#define _PAGE_MA_NAT (0x7 << 2) /* not-a-thing attribute */ |
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#define _PAGE_MA_MASK (0x7 << 2) |
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#define _PAGE_PL_0 (0 << 7) /* privilege level 0 (kernel) */ |
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#define _PAGE_PL_1 (1 << 7) /* privilege level 1 (unused) */ |
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#define _PAGE_PL_2 (2 << 7) /* privilege level 2 (unused) */ |
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#define _PAGE_PL_3 (3 << 7) /* privilege level 3 (user) */ |
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#define _PAGE_PL_MASK (3 << 7) |
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#define _PAGE_AR_R (0 << 9) /* read only */ |
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#define _PAGE_AR_RX (1 << 9) /* read & execute */ |
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#define _PAGE_AR_RW (2 << 9) /* read & write */ |
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#define _PAGE_AR_RWX (3 << 9) /* read, write & execute */ |
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#define _PAGE_AR_R_RW (4 << 9) /* read / read & write */ |
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#define _PAGE_AR_RX_RWX (5 << 9) /* read & exec / read, write & exec */ |
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#define _PAGE_AR_RWX_RW (6 << 9) /* read, write & exec / read & write */ |
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#define _PAGE_AR_X_RX (7 << 9) /* exec & promote / read & exec */ |
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#define _PAGE_AR_MASK (7 << 9) |
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#define _PAGE_AR_SHIFT 9 |
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#define _PAGE_A (1 << _PAGE_A_BIT) /* page accessed bit */ |
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#define _PAGE_D (1 << _PAGE_D_BIT) /* page dirty bit */ |
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#define _PAGE_PPN_MASK (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL) |
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#define _PAGE_ED (__IA64_UL(1) << 52) /* exception deferral */ |
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#define _PAGE_PROTNONE (__IA64_UL(1) << 63) |
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#define _PFN_MASK _PAGE_PPN_MASK |
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/* Mask of bits which may be changed by pte_modify(); the odd bits are there for _PAGE_PROTNONE */ |
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#define _PAGE_CHG_MASK (_PAGE_P | _PAGE_PROTNONE | _PAGE_PL_MASK | _PAGE_AR_MASK | _PAGE_ED) |
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#define _PAGE_SIZE_4K 12 |
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#define _PAGE_SIZE_8K 13 |
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#define _PAGE_SIZE_16K 14 |
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#define _PAGE_SIZE_64K 16 |
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#define _PAGE_SIZE_256K 18 |
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#define _PAGE_SIZE_1M 20 |
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#define _PAGE_SIZE_4M 22 |
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#define _PAGE_SIZE_16M 24 |
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#define _PAGE_SIZE_64M 26 |
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#define _PAGE_SIZE_256M 28 |
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#define _PAGE_SIZE_1G 30 |
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#define _PAGE_SIZE_4G 32 |
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#define __ACCESS_BITS _PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_MA_WB |
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#define __DIRTY_BITS_NO_ED _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB |
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#define __DIRTY_BITS _PAGE_ED | __DIRTY_BITS_NO_ED |
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/* |
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* How many pointers will a page table level hold expressed in shift |
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*/ |
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#define PTRS_PER_PTD_SHIFT (PAGE_SHIFT-3) |
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/* |
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* Definitions for fourth level: |
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*/ |
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#define PTRS_PER_PTE (__IA64_UL(1) << (PTRS_PER_PTD_SHIFT)) |
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/* |
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* Definitions for third level: |
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* |
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* PMD_SHIFT determines the size of the area a third-level page table |
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* can map. |
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*/ |
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#define PMD_SHIFT (PAGE_SHIFT + (PTRS_PER_PTD_SHIFT)) |
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#define PMD_SIZE (1UL << PMD_SHIFT) |
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#define PMD_MASK (~(PMD_SIZE-1)) |
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#define PTRS_PER_PMD (1UL << (PTRS_PER_PTD_SHIFT)) |
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#if CONFIG_PGTABLE_LEVELS == 4 |
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/* |
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* Definitions for second level: |
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* |
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* PUD_SHIFT determines the size of the area a second-level page table |
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* can map. |
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*/ |
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#define PUD_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT)) |
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#define PUD_SIZE (1UL << PUD_SHIFT) |
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#define PUD_MASK (~(PUD_SIZE-1)) |
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#define PTRS_PER_PUD (1UL << (PTRS_PER_PTD_SHIFT)) |
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#endif |
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/* |
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* Definitions for first level: |
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* |
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* PGDIR_SHIFT determines what a first-level page table entry can map. |
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*/ |
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#if CONFIG_PGTABLE_LEVELS == 4 |
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#define PGDIR_SHIFT (PUD_SHIFT + (PTRS_PER_PTD_SHIFT)) |
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#else |
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#define PGDIR_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT)) |
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#endif |
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#define PGDIR_SIZE (__IA64_UL(1) << PGDIR_SHIFT) |
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#define PGDIR_MASK (~(PGDIR_SIZE-1)) |
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#define PTRS_PER_PGD_SHIFT PTRS_PER_PTD_SHIFT |
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#define PTRS_PER_PGD (1UL << PTRS_PER_PGD_SHIFT) |
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#define USER_PTRS_PER_PGD (5*PTRS_PER_PGD/8) /* regions 0-4 are user regions */ |
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/* |
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* All the normal masks have the "page accessed" bits on, as any time |
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* they are used, the page is accessed. They are cleared only by the |
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* page-out routines. |
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*/ |
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#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_A) |
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#define PAGE_SHARED __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW) |
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#define PAGE_READONLY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R) |
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#define PAGE_COPY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R) |
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#define PAGE_COPY_EXEC __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX) |
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#define PAGE_GATE __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX) |
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#define PAGE_KERNEL __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX) |
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#define PAGE_KERNELRX __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX) |
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#define PAGE_KERNEL_UC __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX | \ |
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_PAGE_MA_UC) |
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# ifndef __ASSEMBLY__ |
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#include <linux/sched/mm.h> /* for mm_struct */ |
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#include <linux/bitops.h> |
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#include <asm/cacheflush.h> |
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#include <asm/mmu_context.h> |
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/* |
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* Next come the mappings that determine how mmap() protection bits |
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* (PROT_EXEC, PROT_READ, PROT_WRITE, PROT_NONE) get implemented. The |
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* _P version gets used for a private shared memory segment, the _S |
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* version gets used for a shared memory segment with MAP_SHARED on. |
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* In a private shared memory segment, we do a copy-on-write if a task |
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* attempts to write to the page. |
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*/ |
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/* xwr */ |
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#define __P000 PAGE_NONE |
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#define __P001 PAGE_READONLY |
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#define __P010 PAGE_READONLY /* write to priv pg -> copy & make writable */ |
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#define __P011 PAGE_READONLY /* ditto */ |
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#define __P100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX) |
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#define __P101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX) |
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#define __P110 PAGE_COPY_EXEC |
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#define __P111 PAGE_COPY_EXEC |
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#define __S000 PAGE_NONE |
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#define __S001 PAGE_READONLY |
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#define __S010 PAGE_SHARED /* we don't have (and don't need) write-only */ |
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#define __S011 PAGE_SHARED |
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#define __S100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX) |
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#define __S101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX) |
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#define __S110 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX) |
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#define __S111 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX) |
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#define pgd_ERROR(e) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) |
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#if CONFIG_PGTABLE_LEVELS == 4 |
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#define pud_ERROR(e) printk("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e)) |
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#endif |
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#define pmd_ERROR(e) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) |
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#define pte_ERROR(e) printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) |
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/* |
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* Some definitions to translate between mem_map, PTEs, and page addresses: |
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*/ |
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/* Quick test to see if ADDR is a (potentially) valid physical address. */ |
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static inline long |
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ia64_phys_addr_valid (unsigned long addr) |
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{ |
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return (addr & (local_cpu_data->unimpl_pa_mask)) == 0; |
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} |
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/* |
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* kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel |
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* memory. For the return value to be meaningful, ADDR must be >= |
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* PAGE_OFFSET. This operation can be relatively expensive (e.g., |
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* require a hash-, or multi-level tree-lookup or something of that |
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* sort) but it guarantees to return TRUE only if accessing the page |
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* at that address does not cause an error. Note that there may be |
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* addresses for which kern_addr_valid() returns FALSE even though an |
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* access would not cause an error (e.g., this is typically true for |
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* memory mapped I/O regions. |
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* |
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* XXX Need to implement this for IA-64. |
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*/ |
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#define kern_addr_valid(addr) (1) |
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/* |
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* Now come the defines and routines to manage and access the three-level |
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* page table. |
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*/ |
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#define VMALLOC_START (RGN_BASE(RGN_GATE) + 0x200000000UL) |
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#if defined(CONFIG_SPARSEMEM) && defined(CONFIG_SPARSEMEM_VMEMMAP) |
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/* SPARSEMEM_VMEMMAP uses half of vmalloc... */ |
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# define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 10))) |
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# define vmemmap ((struct page *)VMALLOC_END) |
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#else |
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# define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9))) |
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#endif |
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/* fs/proc/kcore.c */ |
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#define kc_vaddr_to_offset(v) ((v) - RGN_BASE(RGN_GATE)) |
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#define kc_offset_to_vaddr(o) ((o) + RGN_BASE(RGN_GATE)) |
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#define RGN_MAP_SHIFT (PGDIR_SHIFT + PTRS_PER_PGD_SHIFT - 3) |
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#define RGN_MAP_LIMIT ((1UL << RGN_MAP_SHIFT) - PAGE_SIZE) /* per region addr limit */ |
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/* |
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* Conversion functions: convert page frame number (pfn) and a protection value to a page |
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* table entry (pte). |
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*/ |
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#define pfn_pte(pfn, pgprot) \ |
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({ pte_t __pte; pte_val(__pte) = ((pfn) << PAGE_SHIFT) | pgprot_val(pgprot); __pte; }) |
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/* Extract pfn from pte. */ |
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#define pte_pfn(_pte) ((pte_val(_pte) & _PFN_MASK) >> PAGE_SHIFT) |
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#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) |
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/* This takes a physical page address that is used by the remapping functions */ |
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#define mk_pte_phys(physpage, pgprot) \ |
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({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; }) |
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#define pte_modify(_pte, newprot) \ |
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(__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK))) |
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#define pte_none(pte) (!pte_val(pte)) |
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#define pte_present(pte) (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE)) |
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#define pte_clear(mm,addr,pte) (pte_val(*(pte)) = 0UL) |
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/* pte_page() returns the "struct page *" corresponding to the PTE: */ |
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#define pte_page(pte) virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET)) |
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#define pmd_none(pmd) (!pmd_val(pmd)) |
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#define pmd_bad(pmd) (!ia64_phys_addr_valid(pmd_val(pmd))) |
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#define pmd_present(pmd) (pmd_val(pmd) != 0UL) |
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#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL) |
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#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK)) |
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#define pmd_pfn(pmd) ((pmd_val(pmd) & _PFN_MASK) >> PAGE_SHIFT) |
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#define pmd_page(pmd) virt_to_page((pmd_val(pmd) + PAGE_OFFSET)) |
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#define pud_none(pud) (!pud_val(pud)) |
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#define pud_bad(pud) (!ia64_phys_addr_valid(pud_val(pud))) |
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#define pud_present(pud) (pud_val(pud) != 0UL) |
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#define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) |
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#define pud_pgtable(pud) ((pmd_t *) __va(pud_val(pud) & _PFN_MASK)) |
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#define pud_page(pud) virt_to_page((pud_val(pud) + PAGE_OFFSET)) |
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#if CONFIG_PGTABLE_LEVELS == 4 |
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#define p4d_none(p4d) (!p4d_val(p4d)) |
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#define p4d_bad(p4d) (!ia64_phys_addr_valid(p4d_val(p4d))) |
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#define p4d_present(p4d) (p4d_val(p4d) != 0UL) |
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#define p4d_clear(p4dp) (p4d_val(*(p4dp)) = 0UL) |
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#define p4d_pgtable(p4d) ((pud_t *) __va(p4d_val(p4d) & _PFN_MASK)) |
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#define p4d_page(p4d) virt_to_page((p4d_val(p4d) + PAGE_OFFSET)) |
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#endif |
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/* |
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* The following have defined behavior only work if pte_present() is true. |
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*/ |
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#define pte_write(pte) ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4) |
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#define pte_exec(pte) ((pte_val(pte) & _PAGE_AR_RX) != 0) |
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#define pte_dirty(pte) ((pte_val(pte) & _PAGE_D) != 0) |
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#define pte_young(pte) ((pte_val(pte) & _PAGE_A) != 0) |
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/* |
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* Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the |
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* access rights: |
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*/ |
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#define pte_wrprotect(pte) (__pte(pte_val(pte) & ~_PAGE_AR_RW)) |
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#define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_AR_RW)) |
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#define pte_mkold(pte) (__pte(pte_val(pte) & ~_PAGE_A)) |
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#define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_A)) |
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#define pte_mkclean(pte) (__pte(pte_val(pte) & ~_PAGE_D)) |
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#define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D)) |
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#define pte_mkhuge(pte) (__pte(pte_val(pte))) |
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/* |
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* Because ia64's Icache and Dcache is not coherent (on a cpu), we need to |
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* sync icache and dcache when we insert *new* executable page. |
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* __ia64_sync_icache_dcache() check Pg_arch_1 bit and flush icache |
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* if necessary. |
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* |
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* set_pte() is also called by the kernel, but we can expect that the kernel |
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* flushes icache explicitly if necessary. |
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*/ |
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#define pte_present_exec_user(pte)\ |
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((pte_val(pte) & (_PAGE_P | _PAGE_PL_MASK | _PAGE_AR_RX)) == \ |
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(_PAGE_P | _PAGE_PL_3 | _PAGE_AR_RX)) |
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extern void __ia64_sync_icache_dcache(pte_t pteval); |
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static inline void set_pte(pte_t *ptep, pte_t pteval) |
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{ |
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/* page is present && page is user && page is executable |
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* && (page swapin or new page or page migration |
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* || copy_on_write with page copying.) |
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*/ |
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if (pte_present_exec_user(pteval) && |
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(!pte_present(*ptep) || |
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pte_pfn(*ptep) != pte_pfn(pteval))) |
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/* load_module() calles flush_icache_range() explicitly*/ |
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__ia64_sync_icache_dcache(pteval); |
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*ptep = pteval; |
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} |
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#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) |
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/* |
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* Make page protection values cacheable, uncacheable, or write- |
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* combining. Note that "protection" is really a misnomer here as the |
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* protection value contains the memory attribute bits, dirty bits, and |
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* various other bits as well. |
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*/ |
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#define pgprot_cacheable(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WB) |
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#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC) |
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#define pgprot_writecombine(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC) |
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struct file; |
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extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, |
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unsigned long size, pgprot_t vma_prot); |
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#define __HAVE_PHYS_MEM_ACCESS_PROT |
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static inline unsigned long |
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pgd_index (unsigned long address) |
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{ |
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unsigned long region = address >> 61; |
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unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1); |
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return (region << (PAGE_SHIFT - 6)) | l1index; |
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} |
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#define pgd_index pgd_index |
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/* |
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* In the kernel's mapped region we know everything is in region number 5, so |
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* as an optimisation its PGD already points to the area for that region. |
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* However, this also means that we cannot use pgd_index() and we must |
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* never add the region here. |
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*/ |
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#define pgd_offset_k(addr) \ |
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(init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))) |
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/* Look up a pgd entry in the gate area. On IA-64, the gate-area |
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resides in the kernel-mapped segment, hence we use pgd_offset_k() |
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here. */ |
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#define pgd_offset_gate(mm, addr) pgd_offset_k(addr) |
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/* atomic versions of the some PTE manipulations: */ |
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static inline int |
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ptep_test_and_clear_young (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) |
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{ |
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#ifdef CONFIG_SMP |
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if (!pte_young(*ptep)) |
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return 0; |
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return test_and_clear_bit(_PAGE_A_BIT, ptep); |
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#else |
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pte_t pte = *ptep; |
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if (!pte_young(pte)) |
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return 0; |
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set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte)); |
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return 1; |
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#endif |
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} |
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static inline pte_t |
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ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) |
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{ |
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#ifdef CONFIG_SMP |
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return __pte(xchg((long *) ptep, 0)); |
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#else |
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pte_t pte = *ptep; |
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pte_clear(mm, addr, ptep); |
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return pte; |
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#endif |
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} |
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static inline void |
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ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) |
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{ |
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#ifdef CONFIG_SMP |
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unsigned long new, old; |
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do { |
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old = pte_val(*ptep); |
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new = pte_val(pte_wrprotect(__pte (old))); |
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} while (cmpxchg((unsigned long *) ptep, old, new) != old); |
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#else |
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pte_t old_pte = *ptep; |
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set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte)); |
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#endif |
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} |
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static inline int |
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pte_same (pte_t a, pte_t b) |
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{ |
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return pte_val(a) == pte_val(b); |
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} |
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#define update_mmu_cache(vma, address, ptep) do { } while (0) |
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extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; |
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extern void paging_init (void); |
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/* |
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* Note: The macros below rely on the fact that MAX_SWAPFILES_SHIFT <= number of |
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* bits in the swap-type field of the swap pte. It would be nice to |
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* enforce that, but we can't easily include <linux/swap.h> here. |
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* (Of course, better still would be to define MAX_SWAPFILES_SHIFT here...). |
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* |
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* Format of swap pte: |
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* bit 0 : present bit (must be zero) |
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* bits 1- 7: swap-type |
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* bits 8-62: swap offset |
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* bit 63 : _PAGE_PROTNONE bit |
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*/ |
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#define __swp_type(entry) (((entry).val >> 1) & 0x7f) |
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#define __swp_offset(entry) (((entry).val << 1) >> 9) |
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#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 1) | ((long) (offset) << 8) }) |
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) |
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) |
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/* |
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* ZERO_PAGE is a global shared page that is always zero: used |
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* for zero-mapped memory areas etc.. |
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*/ |
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extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)]; |
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extern struct page *zero_page_memmap_ptr; |
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#define ZERO_PAGE(vaddr) (zero_page_memmap_ptr) |
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/* We provide our own get_unmapped_area to cope with VA holes for userland */ |
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#define HAVE_ARCH_UNMAPPED_AREA |
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#ifdef CONFIG_HUGETLB_PAGE |
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#define HUGETLB_PGDIR_SHIFT (HPAGE_SHIFT + 2*(PAGE_SHIFT-3)) |
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#define HUGETLB_PGDIR_SIZE (__IA64_UL(1) << HUGETLB_PGDIR_SHIFT) |
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#define HUGETLB_PGDIR_MASK (~(HUGETLB_PGDIR_SIZE-1)) |
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#endif |
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#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS |
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/* |
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* Update PTEP with ENTRY, which is guaranteed to be a less |
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* restrictive PTE. That is, ENTRY may have the ACCESSED, DIRTY, and |
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* WRITABLE bits turned on, when the value at PTEP did not. The |
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* WRITABLE bit may only be turned if SAFELY_WRITABLE is TRUE. |
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* |
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* SAFELY_WRITABLE is TRUE if we can update the value at PTEP without |
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* having to worry about races. On SMP machines, there are only two |
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* cases where this is true: |
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* |
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* (1) *PTEP has the PRESENT bit turned OFF |
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* (2) ENTRY has the DIRTY bit turned ON |
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* |
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* On ia64, we could implement this routine with a cmpxchg()-loop |
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* which ORs in the _PAGE_A/_PAGE_D bit if they're set in ENTRY. |
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* However, like on x86, we can get a more streamlined version by |
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* observing that it is OK to drop ACCESSED bit updates when |
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* SAFELY_WRITABLE is FALSE. Besides being rare, all that would do is |
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* result in an extra Access-bit fault, which would then turn on the |
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* ACCESSED bit in the low-level fault handler (iaccess_bit or |
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* daccess_bit in ivt.S). |
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*/ |
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#ifdef CONFIG_SMP |
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# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \ |
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({ \ |
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int __changed = !pte_same(*(__ptep), __entry); \ |
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if (__changed && __safely_writable) { \ |
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set_pte(__ptep, __entry); \ |
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flush_tlb_page(__vma, __addr); \ |
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} \ |
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__changed; \ |
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}) |
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#else |
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# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \ |
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({ \ |
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int __changed = !pte_same(*(__ptep), __entry); \ |
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if (__changed) { \ |
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set_pte_at((__vma)->vm_mm, (__addr), __ptep, __entry); \ |
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flush_tlb_page(__vma, __addr); \ |
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} \ |
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__changed; \ |
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}) |
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#endif |
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# endif /* !__ASSEMBLY__ */ |
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/* |
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* Identity-mapped regions use a large page size. We'll call such large pages |
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* "granules". If you can think of a better name that's unambiguous, let me |
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* know... |
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*/ |
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#if defined(CONFIG_IA64_GRANULE_64MB) |
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# define IA64_GRANULE_SHIFT _PAGE_SIZE_64M |
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#elif defined(CONFIG_IA64_GRANULE_16MB) |
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# define IA64_GRANULE_SHIFT _PAGE_SIZE_16M |
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#endif |
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#define IA64_GRANULE_SIZE (1 << IA64_GRANULE_SHIFT) |
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/* |
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* log2() of the page size we use to map the kernel image (IA64_TR_KERNEL): |
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*/ |
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#define KERNEL_TR_PAGE_SHIFT _PAGE_SIZE_64M |
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#define KERNEL_TR_PAGE_SIZE (1 << KERNEL_TR_PAGE_SHIFT) |
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/* These tell get_user_pages() that the first gate page is accessible from user-level. */ |
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#define FIXADDR_USER_START GATE_ADDR |
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#ifdef HAVE_BUGGY_SEGREL |
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# define FIXADDR_USER_END (GATE_ADDR + 2*PAGE_SIZE) |
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#else |
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# define FIXADDR_USER_END (GATE_ADDR + 2*PERCPU_PAGE_SIZE) |
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#endif |
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#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG |
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#define __HAVE_ARCH_PTEP_GET_AND_CLEAR |
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#define __HAVE_ARCH_PTEP_SET_WRPROTECT |
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#define __HAVE_ARCH_PTE_SAME |
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#define __HAVE_ARCH_PGD_OFFSET_GATE |
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#if CONFIG_PGTABLE_LEVELS == 3 |
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#include <asm-generic/pgtable-nopud.h> |
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#endif |
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#include <asm-generic/pgtable-nop4d.h> |
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#endif /* _ASM_IA64_PGTABLE_H */
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