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107 lines
2.5 KiB
107 lines
2.5 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* reset controller for CSR SiRFprimaII |
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* |
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/mutex.h> |
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#include <linux/io.h> |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/platform_device.h> |
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#include <linux/reboot.h> |
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#include <linux/reset-controller.h> |
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#include <asm/system_misc.h> |
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#define SIRFSOC_RSTBIT_NUM 64 |
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static void __iomem *sirfsoc_rstc_base; |
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static DEFINE_MUTEX(rstc_lock); |
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static int sirfsoc_reset_module(struct reset_controller_dev *rcdev, |
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unsigned long sw_reset_idx) |
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{ |
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u32 reset_bit = sw_reset_idx; |
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if (reset_bit >= SIRFSOC_RSTBIT_NUM) |
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return -EINVAL; |
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mutex_lock(&rstc_lock); |
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/* |
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* Writing 1 to this bit resets corresponding block. |
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* Writing 0 to this bit de-asserts reset signal of the |
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* corresponding block. datasheet doesn't require explicit |
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* delay between the set and clear of reset bit. it could |
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* be shorter if tests pass. |
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*/ |
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writel(readl(sirfsoc_rstc_base + |
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(reset_bit / 32) * 4) | (1 << reset_bit), |
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sirfsoc_rstc_base + (reset_bit / 32) * 4); |
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msleep(20); |
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writel(readl(sirfsoc_rstc_base + |
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(reset_bit / 32) * 4) & ~(1 << reset_bit), |
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sirfsoc_rstc_base + (reset_bit / 32) * 4); |
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mutex_unlock(&rstc_lock); |
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return 0; |
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} |
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static struct reset_control_ops sirfsoc_rstc_ops = { |
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.reset = sirfsoc_reset_module, |
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}; |
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static struct reset_controller_dev sirfsoc_reset_controller = { |
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.ops = &sirfsoc_rstc_ops, |
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.nr_resets = SIRFSOC_RSTBIT_NUM, |
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}; |
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#define SIRFSOC_SYS_RST_BIT BIT(31) |
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static void sirfsoc_restart(enum reboot_mode mode, const char *cmd) |
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{ |
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writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base); |
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} |
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static int sirfsoc_rstc_probe(struct platform_device *pdev) |
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{ |
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struct device_node *np = pdev->dev.of_node; |
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sirfsoc_rstc_base = of_iomap(np, 0); |
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if (!sirfsoc_rstc_base) { |
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dev_err(&pdev->dev, "unable to map rstc cpu registers\n"); |
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return -ENOMEM; |
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} |
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sirfsoc_reset_controller.of_node = np; |
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arm_pm_restart = sirfsoc_restart; |
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if (IS_ENABLED(CONFIG_RESET_CONTROLLER)) |
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reset_controller_register(&sirfsoc_reset_controller); |
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return 0; |
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} |
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static const struct of_device_id rstc_ids[] = { |
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{ .compatible = "sirf,prima2-rstc" }, |
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{}, |
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}; |
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static struct platform_driver sirfsoc_rstc_driver = { |
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.probe = sirfsoc_rstc_probe, |
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.driver = { |
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.name = "sirfsoc_rstc", |
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.of_match_table = rstc_ids, |
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}, |
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}; |
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static int __init sirfsoc_rstc_init(void) |
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{ |
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return platform_driver_register(&sirfsoc_rstc_driver); |
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} |
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subsys_initcall(sirfsoc_rstc_init);
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