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602 lines
15 KiB
602 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright 2017 NXP |
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* Copyright 2011,2016 Freescale Semiconductor, Inc. |
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* Copyright 2011 Linaro Ltd. |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/hrtimer.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/perf_event.h> |
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#include <linux/slab.h> |
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#include "common.h" |
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|
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#define MMDC_MAPSR 0x404 |
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#define BP_MMDC_MAPSR_PSD 0 |
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#define BP_MMDC_MAPSR_PSS 4 |
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#define MMDC_MDMISC 0x18 |
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#define BM_MMDC_MDMISC_DDR_TYPE 0x18 |
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#define BP_MMDC_MDMISC_DDR_TYPE 0x3 |
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#define TOTAL_CYCLES 0x0 |
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#define BUSY_CYCLES 0x1 |
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#define READ_ACCESSES 0x2 |
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#define WRITE_ACCESSES 0x3 |
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#define READ_BYTES 0x4 |
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#define WRITE_BYTES 0x5 |
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/* Enables, resets, freezes, overflow profiling*/ |
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#define DBG_DIS 0x0 |
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#define DBG_EN 0x1 |
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#define DBG_RST 0x2 |
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#define PRF_FRZ 0x4 |
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#define CYC_OVF 0x8 |
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#define PROFILE_SEL 0x10 |
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#define MMDC_MADPCR0 0x410 |
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#define MMDC_MADPCR1 0x414 |
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#define MMDC_MADPSR0 0x418 |
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#define MMDC_MADPSR1 0x41C |
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#define MMDC_MADPSR2 0x420 |
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#define MMDC_MADPSR3 0x424 |
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#define MMDC_MADPSR4 0x428 |
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#define MMDC_MADPSR5 0x42C |
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#define MMDC_NUM_COUNTERS 6 |
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#define MMDC_FLAG_PROFILE_SEL 0x1 |
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#define MMDC_PRF_AXI_ID_CLEAR 0x0 |
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#define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu) |
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static int ddr_type; |
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struct fsl_mmdc_devtype_data { |
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unsigned int flags; |
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}; |
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static const struct fsl_mmdc_devtype_data imx6q_data = { |
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}; |
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static const struct fsl_mmdc_devtype_data imx6qp_data = { |
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.flags = MMDC_FLAG_PROFILE_SEL, |
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}; |
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static const struct of_device_id imx_mmdc_dt_ids[] = { |
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{ .compatible = "fsl,imx6q-mmdc", .data = (void *)&imx6q_data}, |
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{ .compatible = "fsl,imx6qp-mmdc", .data = (void *)&imx6qp_data}, |
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{ /* sentinel */ } |
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}; |
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#ifdef CONFIG_PERF_EVENTS |
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static enum cpuhp_state cpuhp_mmdc_state; |
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static DEFINE_IDA(mmdc_ida); |
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PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00") |
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PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01") |
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PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02") |
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PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "event=0x03") |
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PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04") |
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PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB"); |
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PMU_EVENT_ATTR_STRING(read-bytes.scale, mmdc_pmu_read_bytes_scale, "0.000001"); |
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PMU_EVENT_ATTR_STRING(write-bytes, mmdc_pmu_write_bytes, "event=0x05") |
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PMU_EVENT_ATTR_STRING(write-bytes.unit, mmdc_pmu_write_bytes_unit, "MB"); |
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PMU_EVENT_ATTR_STRING(write-bytes.scale, mmdc_pmu_write_bytes_scale, "0.000001"); |
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struct mmdc_pmu { |
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struct pmu pmu; |
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void __iomem *mmdc_base; |
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cpumask_t cpu; |
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struct hrtimer hrtimer; |
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unsigned int active_events; |
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struct device *dev; |
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struct perf_event *mmdc_events[MMDC_NUM_COUNTERS]; |
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struct hlist_node node; |
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struct fsl_mmdc_devtype_data *devtype_data; |
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struct clk *mmdc_ipg_clk; |
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}; |
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/* |
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* Polling period is set to one second, overflow of total-cycles (the fastest |
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* increasing counter) takes ten seconds so one second is safe |
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*/ |
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static unsigned int mmdc_pmu_poll_period_us = 1000000; |
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module_param_named(pmu_pmu_poll_period_us, mmdc_pmu_poll_period_us, uint, |
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S_IRUGO | S_IWUSR); |
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static ktime_t mmdc_pmu_timer_period(void) |
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{ |
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return ns_to_ktime((u64)mmdc_pmu_poll_period_us * 1000); |
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} |
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static ssize_t mmdc_pmu_cpumask_show(struct device *dev, |
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struct device_attribute *attr, char *buf) |
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{ |
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struct mmdc_pmu *pmu_mmdc = dev_get_drvdata(dev); |
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return cpumap_print_to_pagebuf(true, buf, &pmu_mmdc->cpu); |
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} |
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static struct device_attribute mmdc_pmu_cpumask_attr = |
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__ATTR(cpumask, S_IRUGO, mmdc_pmu_cpumask_show, NULL); |
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static struct attribute *mmdc_pmu_cpumask_attrs[] = { |
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&mmdc_pmu_cpumask_attr.attr, |
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NULL, |
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}; |
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static struct attribute_group mmdc_pmu_cpumask_attr_group = { |
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.attrs = mmdc_pmu_cpumask_attrs, |
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}; |
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static struct attribute *mmdc_pmu_events_attrs[] = { |
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&mmdc_pmu_total_cycles.attr.attr, |
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&mmdc_pmu_busy_cycles.attr.attr, |
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&mmdc_pmu_read_accesses.attr.attr, |
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&mmdc_pmu_write_accesses.attr.attr, |
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&mmdc_pmu_read_bytes.attr.attr, |
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&mmdc_pmu_read_bytes_unit.attr.attr, |
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&mmdc_pmu_read_bytes_scale.attr.attr, |
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&mmdc_pmu_write_bytes.attr.attr, |
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&mmdc_pmu_write_bytes_unit.attr.attr, |
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&mmdc_pmu_write_bytes_scale.attr.attr, |
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NULL, |
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}; |
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static struct attribute_group mmdc_pmu_events_attr_group = { |
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.name = "events", |
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.attrs = mmdc_pmu_events_attrs, |
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}; |
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PMU_FORMAT_ATTR(event, "config:0-63"); |
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PMU_FORMAT_ATTR(axi_id, "config1:0-63"); |
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static struct attribute *mmdc_pmu_format_attrs[] = { |
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&format_attr_event.attr, |
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&format_attr_axi_id.attr, |
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NULL, |
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}; |
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static struct attribute_group mmdc_pmu_format_attr_group = { |
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.name = "format", |
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.attrs = mmdc_pmu_format_attrs, |
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}; |
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static const struct attribute_group *attr_groups[] = { |
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&mmdc_pmu_events_attr_group, |
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&mmdc_pmu_format_attr_group, |
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&mmdc_pmu_cpumask_attr_group, |
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NULL, |
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}; |
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static u32 mmdc_pmu_read_counter(struct mmdc_pmu *pmu_mmdc, int cfg) |
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{ |
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void __iomem *mmdc_base, *reg; |
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mmdc_base = pmu_mmdc->mmdc_base; |
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switch (cfg) { |
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case TOTAL_CYCLES: |
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reg = mmdc_base + MMDC_MADPSR0; |
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break; |
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case BUSY_CYCLES: |
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reg = mmdc_base + MMDC_MADPSR1; |
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break; |
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case READ_ACCESSES: |
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reg = mmdc_base + MMDC_MADPSR2; |
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break; |
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case WRITE_ACCESSES: |
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reg = mmdc_base + MMDC_MADPSR3; |
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break; |
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case READ_BYTES: |
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reg = mmdc_base + MMDC_MADPSR4; |
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break; |
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case WRITE_BYTES: |
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reg = mmdc_base + MMDC_MADPSR5; |
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break; |
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default: |
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return WARN_ONCE(1, |
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"invalid configuration %d for mmdc counter", cfg); |
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} |
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return readl(reg); |
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} |
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static int mmdc_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) |
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{ |
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struct mmdc_pmu *pmu_mmdc = hlist_entry_safe(node, struct mmdc_pmu, node); |
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int target; |
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if (!cpumask_test_and_clear_cpu(cpu, &pmu_mmdc->cpu)) |
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return 0; |
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target = cpumask_any_but(cpu_online_mask, cpu); |
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if (target >= nr_cpu_ids) |
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return 0; |
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perf_pmu_migrate_context(&pmu_mmdc->pmu, cpu, target); |
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cpumask_set_cpu(target, &pmu_mmdc->cpu); |
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return 0; |
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} |
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static bool mmdc_pmu_group_event_is_valid(struct perf_event *event, |
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struct pmu *pmu, |
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unsigned long *used_counters) |
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{ |
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int cfg = event->attr.config; |
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if (is_software_event(event)) |
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return true; |
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if (event->pmu != pmu) |
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return false; |
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return !test_and_set_bit(cfg, used_counters); |
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} |
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/* |
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* Each event has a single fixed-purpose counter, so we can only have a |
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* single active event for each at any point in time. Here we just check |
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* for duplicates, and rely on mmdc_pmu_event_init to verify that the HW |
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* event numbers are valid. |
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*/ |
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static bool mmdc_pmu_group_is_valid(struct perf_event *event) |
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{ |
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struct pmu *pmu = event->pmu; |
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struct perf_event *leader = event->group_leader; |
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struct perf_event *sibling; |
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unsigned long counter_mask = 0; |
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set_bit(leader->attr.config, &counter_mask); |
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if (event != leader) { |
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if (!mmdc_pmu_group_event_is_valid(event, pmu, &counter_mask)) |
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return false; |
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} |
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for_each_sibling_event(sibling, leader) { |
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if (!mmdc_pmu_group_event_is_valid(sibling, pmu, &counter_mask)) |
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return false; |
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} |
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return true; |
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} |
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static int mmdc_pmu_event_init(struct perf_event *event) |
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{ |
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struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); |
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int cfg = event->attr.config; |
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if (event->attr.type != event->pmu->type) |
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return -ENOENT; |
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if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) |
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return -EOPNOTSUPP; |
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if (event->cpu < 0) { |
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dev_warn(pmu_mmdc->dev, "Can't provide per-task data!\n"); |
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return -EOPNOTSUPP; |
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} |
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if (event->attr.sample_period) |
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return -EINVAL; |
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if (cfg < 0 || cfg >= MMDC_NUM_COUNTERS) |
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return -EINVAL; |
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if (!mmdc_pmu_group_is_valid(event)) |
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return -EINVAL; |
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event->cpu = cpumask_first(&pmu_mmdc->cpu); |
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return 0; |
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} |
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static void mmdc_pmu_event_update(struct perf_event *event) |
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{ |
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struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); |
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struct hw_perf_event *hwc = &event->hw; |
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u64 delta, prev_raw_count, new_raw_count; |
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do { |
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prev_raw_count = local64_read(&hwc->prev_count); |
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new_raw_count = mmdc_pmu_read_counter(pmu_mmdc, |
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event->attr.config); |
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} while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
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new_raw_count) != prev_raw_count); |
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delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF; |
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local64_add(delta, &event->count); |
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} |
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static void mmdc_pmu_event_start(struct perf_event *event, int flags) |
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{ |
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struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); |
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struct hw_perf_event *hwc = &event->hw; |
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void __iomem *mmdc_base, *reg; |
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u32 val; |
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mmdc_base = pmu_mmdc->mmdc_base; |
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reg = mmdc_base + MMDC_MADPCR0; |
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/* |
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* hrtimer is required because mmdc does not provide an interrupt so |
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* polling is necessary |
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*/ |
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hrtimer_start(&pmu_mmdc->hrtimer, mmdc_pmu_timer_period(), |
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HRTIMER_MODE_REL_PINNED); |
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local64_set(&hwc->prev_count, 0); |
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writel(DBG_RST, reg); |
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/* |
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* Write the AXI id parameter to MADPCR1. |
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*/ |
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val = event->attr.config1; |
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reg = mmdc_base + MMDC_MADPCR1; |
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writel(val, reg); |
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reg = mmdc_base + MMDC_MADPCR0; |
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val = DBG_EN; |
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if (pmu_mmdc->devtype_data->flags & MMDC_FLAG_PROFILE_SEL) |
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val |= PROFILE_SEL; |
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writel(val, reg); |
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} |
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static int mmdc_pmu_event_add(struct perf_event *event, int flags) |
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{ |
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struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); |
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struct hw_perf_event *hwc = &event->hw; |
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int cfg = event->attr.config; |
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if (flags & PERF_EF_START) |
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mmdc_pmu_event_start(event, flags); |
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if (pmu_mmdc->mmdc_events[cfg] != NULL) |
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return -EAGAIN; |
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pmu_mmdc->mmdc_events[cfg] = event; |
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pmu_mmdc->active_events++; |
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local64_set(&hwc->prev_count, mmdc_pmu_read_counter(pmu_mmdc, cfg)); |
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return 0; |
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} |
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static void mmdc_pmu_event_stop(struct perf_event *event, int flags) |
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{ |
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struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); |
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void __iomem *mmdc_base, *reg; |
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mmdc_base = pmu_mmdc->mmdc_base; |
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reg = mmdc_base + MMDC_MADPCR0; |
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writel(PRF_FRZ, reg); |
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reg = mmdc_base + MMDC_MADPCR1; |
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writel(MMDC_PRF_AXI_ID_CLEAR, reg); |
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mmdc_pmu_event_update(event); |
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} |
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static void mmdc_pmu_event_del(struct perf_event *event, int flags) |
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{ |
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struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); |
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int cfg = event->attr.config; |
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pmu_mmdc->mmdc_events[cfg] = NULL; |
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pmu_mmdc->active_events--; |
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if (pmu_mmdc->active_events == 0) |
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hrtimer_cancel(&pmu_mmdc->hrtimer); |
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mmdc_pmu_event_stop(event, PERF_EF_UPDATE); |
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} |
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static void mmdc_pmu_overflow_handler(struct mmdc_pmu *pmu_mmdc) |
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{ |
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int i; |
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for (i = 0; i < MMDC_NUM_COUNTERS; i++) { |
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struct perf_event *event = pmu_mmdc->mmdc_events[i]; |
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if (event) |
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mmdc_pmu_event_update(event); |
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} |
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} |
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static enum hrtimer_restart mmdc_pmu_timer_handler(struct hrtimer *hrtimer) |
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{ |
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struct mmdc_pmu *pmu_mmdc = container_of(hrtimer, struct mmdc_pmu, |
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hrtimer); |
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mmdc_pmu_overflow_handler(pmu_mmdc); |
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hrtimer_forward_now(hrtimer, mmdc_pmu_timer_period()); |
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return HRTIMER_RESTART; |
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} |
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static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc, |
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void __iomem *mmdc_base, struct device *dev) |
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{ |
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int mmdc_num; |
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*pmu_mmdc = (struct mmdc_pmu) { |
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.pmu = (struct pmu) { |
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.task_ctx_nr = perf_invalid_context, |
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.attr_groups = attr_groups, |
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.event_init = mmdc_pmu_event_init, |
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.add = mmdc_pmu_event_add, |
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.del = mmdc_pmu_event_del, |
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.start = mmdc_pmu_event_start, |
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.stop = mmdc_pmu_event_stop, |
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.read = mmdc_pmu_event_update, |
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.capabilities = PERF_PMU_CAP_NO_EXCLUDE, |
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}, |
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.mmdc_base = mmdc_base, |
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.dev = dev, |
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.active_events = 0, |
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}; |
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mmdc_num = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL); |
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return mmdc_num; |
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} |
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static int imx_mmdc_remove(struct platform_device *pdev) |
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{ |
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struct mmdc_pmu *pmu_mmdc = platform_get_drvdata(pdev); |
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cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); |
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perf_pmu_unregister(&pmu_mmdc->pmu); |
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iounmap(pmu_mmdc->mmdc_base); |
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clk_disable_unprepare(pmu_mmdc->mmdc_ipg_clk); |
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kfree(pmu_mmdc); |
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return 0; |
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} |
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static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_base, |
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struct clk *mmdc_ipg_clk) |
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{ |
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struct mmdc_pmu *pmu_mmdc; |
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char *name; |
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int mmdc_num; |
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int ret; |
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const struct of_device_id *of_id = |
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of_match_device(imx_mmdc_dt_ids, &pdev->dev); |
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pmu_mmdc = kzalloc(sizeof(*pmu_mmdc), GFP_KERNEL); |
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if (!pmu_mmdc) { |
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pr_err("failed to allocate PMU device!\n"); |
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return -ENOMEM; |
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} |
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/* The first instance registers the hotplug state */ |
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if (!cpuhp_mmdc_state) { |
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ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, |
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"perf/arm/mmdc:online", NULL, |
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mmdc_pmu_offline_cpu); |
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if (ret < 0) { |
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pr_err("cpuhp_setup_state_multi failed\n"); |
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goto pmu_free; |
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} |
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cpuhp_mmdc_state = ret; |
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} |
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mmdc_num = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev); |
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pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk; |
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if (mmdc_num == 0) |
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name = "mmdc"; |
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else |
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name = devm_kasprintf(&pdev->dev, |
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GFP_KERNEL, "mmdc%d", mmdc_num); |
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pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data; |
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hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC, |
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HRTIMER_MODE_REL); |
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pmu_mmdc->hrtimer.function = mmdc_pmu_timer_handler; |
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cpumask_set_cpu(raw_smp_processor_id(), &pmu_mmdc->cpu); |
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/* Register the pmu instance for cpu hotplug */ |
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cpuhp_state_add_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); |
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ret = perf_pmu_register(&(pmu_mmdc->pmu), name, -1); |
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if (ret) |
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goto pmu_register_err; |
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|
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platform_set_drvdata(pdev, pmu_mmdc); |
|
return 0; |
|
|
|
pmu_register_err: |
|
pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret); |
|
cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); |
|
hrtimer_cancel(&pmu_mmdc->hrtimer); |
|
pmu_free: |
|
kfree(pmu_mmdc); |
|
return ret; |
|
} |
|
|
|
#else |
|
#define imx_mmdc_remove NULL |
|
#define imx_mmdc_perf_init(pdev, mmdc_base, mmdc_ipg_clk) 0 |
|
#endif |
|
|
|
static int imx_mmdc_probe(struct platform_device *pdev) |
|
{ |
|
struct device_node *np = pdev->dev.of_node; |
|
void __iomem *mmdc_base, *reg; |
|
struct clk *mmdc_ipg_clk; |
|
u32 val; |
|
int err; |
|
|
|
/* the ipg clock is optional */ |
|
mmdc_ipg_clk = devm_clk_get(&pdev->dev, NULL); |
|
if (IS_ERR(mmdc_ipg_clk)) |
|
mmdc_ipg_clk = NULL; |
|
|
|
err = clk_prepare_enable(mmdc_ipg_clk); |
|
if (err) { |
|
dev_err(&pdev->dev, "Unable to enable mmdc ipg clock.\n"); |
|
return err; |
|
} |
|
|
|
mmdc_base = of_iomap(np, 0); |
|
WARN_ON(!mmdc_base); |
|
|
|
reg = mmdc_base + MMDC_MDMISC; |
|
/* Get ddr type */ |
|
val = readl_relaxed(reg); |
|
ddr_type = (val & BM_MMDC_MDMISC_DDR_TYPE) >> |
|
BP_MMDC_MDMISC_DDR_TYPE; |
|
|
|
reg = mmdc_base + MMDC_MAPSR; |
|
|
|
/* Enable automatic power saving */ |
|
val = readl_relaxed(reg); |
|
val &= ~(1 << BP_MMDC_MAPSR_PSD); |
|
writel_relaxed(val, reg); |
|
|
|
err = imx_mmdc_perf_init(pdev, mmdc_base, mmdc_ipg_clk); |
|
if (err) { |
|
iounmap(mmdc_base); |
|
clk_disable_unprepare(mmdc_ipg_clk); |
|
} |
|
|
|
return err; |
|
} |
|
|
|
int imx_mmdc_get_ddr_type(void) |
|
{ |
|
return ddr_type; |
|
} |
|
|
|
static struct platform_driver imx_mmdc_driver = { |
|
.driver = { |
|
.name = "imx-mmdc", |
|
.of_match_table = imx_mmdc_dt_ids, |
|
}, |
|
.probe = imx_mmdc_probe, |
|
.remove = imx_mmdc_remove, |
|
}; |
|
|
|
static int __init imx_mmdc_init(void) |
|
{ |
|
return platform_driver_register(&imx_mmdc_driver); |
|
} |
|
postcore_initcall(imx_mmdc_init);
|
|
|