forked from Qortal/Brooklyn
a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
62 lines
1.6 KiB
C
62 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
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//
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// Authors: Cezary Rojewski <cezary.rojewski@intel.com>
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// Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
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//
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// Special thanks to:
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// Krzysztof Hejmowski <krzysztof.hejmowski@intel.com>
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// Michal Sienkiewicz <michal.sienkiewicz@intel.com>
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// Filip Proborszcz
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//
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// for sharing Intel AudioDSP expertise and helping shape the very
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// foundation of this driver
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//
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#include <linux/pci.h>
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#include <sound/hdaudio.h>
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#include "avs.h"
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static void
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avs_hda_update_config_dword(struct hdac_bus *bus, u32 reg, u32 mask, u32 value)
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{
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struct pci_dev *pci = to_pci_dev(bus->dev);
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u32 data;
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pci_read_config_dword(pci, reg, &data);
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data &= ~mask;
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data |= (value & mask);
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pci_write_config_dword(pci, reg, data);
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}
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void avs_hda_power_gating_enable(struct avs_dev *adev, bool enable)
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{
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u32 value;
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value = enable ? 0 : AZX_PGCTL_LSRMD_MASK;
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avs_hda_update_config_dword(&adev->base.core, AZX_PCIREG_PGCTL,
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AZX_PGCTL_LSRMD_MASK, value);
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}
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static void avs_hdac_clock_gating_enable(struct hdac_bus *bus, bool enable)
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{
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u32 value;
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value = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0;
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avs_hda_update_config_dword(bus, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, value);
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}
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void avs_hda_clock_gating_enable(struct avs_dev *adev, bool enable)
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{
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avs_hdac_clock_gating_enable(&adev->base.core, enable);
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}
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void avs_hda_l1sen_enable(struct avs_dev *adev, bool enable)
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{
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u32 value;
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value = enable ? AZX_VS_EM2_L1SEN : 0;
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snd_hdac_chip_updatel(&adev->base.core, VS_EM2, AZX_VS_EM2_L1SEN, value);
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}
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