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103 lines
2.8 KiB
103 lines
2.8 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* |
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* Parts of this file are based on Ralink's 2.6.21 BSP |
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* |
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* Copyright (C) 2008 Imre Kaloz <[email protected]> |
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* Copyright (C) 2008-2011 Gabor Juhos <[email protected]> |
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* Copyright (C) 2013 John Crispin <[email protected]> |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <asm/mipsregs.h> |
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#include <asm/mach-ralink/ralink_regs.h> |
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#include <asm/mach-ralink/rt3883.h> |
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#include "common.h" |
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void __init ralink_clk_init(void) |
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{ |
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unsigned long cpu_rate, sys_rate; |
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u32 syscfg0; |
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u32 clksel; |
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u32 ddr2; |
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syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0); |
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clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) & |
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RT3883_SYSCFG0_CPUCLK_MASK); |
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ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2; |
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switch (clksel) { |
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case RT3883_SYSCFG0_CPUCLK_250: |
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cpu_rate = 250000000; |
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sys_rate = (ddr2) ? 125000000 : 83000000; |
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break; |
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case RT3883_SYSCFG0_CPUCLK_384: |
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cpu_rate = 384000000; |
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sys_rate = (ddr2) ? 128000000 : 96000000; |
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break; |
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case RT3883_SYSCFG0_CPUCLK_480: |
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cpu_rate = 480000000; |
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sys_rate = (ddr2) ? 160000000 : 120000000; |
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break; |
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case RT3883_SYSCFG0_CPUCLK_500: |
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cpu_rate = 500000000; |
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sys_rate = (ddr2) ? 166000000 : 125000000; |
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break; |
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} |
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ralink_clk_add("cpu", cpu_rate); |
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ralink_clk_add("10000100.timer", sys_rate); |
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ralink_clk_add("10000120.watchdog", sys_rate); |
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ralink_clk_add("10000500.uart", 40000000); |
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ralink_clk_add("10000900.i2c", 40000000); |
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ralink_clk_add("10000a00.i2s", 40000000); |
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ralink_clk_add("10000b00.spi", sys_rate); |
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ralink_clk_add("10000b40.spi", sys_rate); |
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ralink_clk_add("10000c00.uartlite", 40000000); |
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ralink_clk_add("10100000.ethernet", sys_rate); |
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ralink_clk_add("10180000.wmac", 40000000); |
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} |
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void __init ralink_of_remap(void) |
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{ |
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rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc"); |
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rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc"); |
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if (!rt_sysc_membase || !rt_memc_membase) |
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panic("Failed to remap core resources"); |
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} |
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void __init prom_soc_init(struct ralink_soc_info *soc_info) |
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{ |
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void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE); |
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const char *name; |
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u32 n0; |
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u32 n1; |
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u32 id; |
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n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3); |
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n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7); |
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id = __raw_readl(sysc + RT3883_SYSC_REG_REVID); |
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if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) { |
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soc_info->compatible = "ralink,rt3883-soc"; |
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name = "RT3883"; |
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} else { |
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panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1); |
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} |
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snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, |
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"Ralink %s ver:%u eco:%u", |
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name, |
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(id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK, |
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(id & RT3883_REVID_ECO_ID_MASK)); |
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soc_info->mem_base = RT3883_SDRAM_BASE; |
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soc_info->mem_size_min = RT3883_MEM_SIZE_MIN; |
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soc_info->mem_size_max = RT3883_MEM_SIZE_MAX; |
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ralink_soc = RT3883_SOC; |
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}
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