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298 lines
6.9 KiB
298 lines
6.9 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2015 Microchip Technology Inc. All rights reserved. |
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*/ |
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#include <dt-bindings/clock/microchip,pic32-clock.h> |
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#include <dt-bindings/interrupt-controller/irq.h> |
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/ { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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interrupt-parent = <&evic>; |
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aliases { |
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gpio0 = &gpio0; |
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gpio1 = &gpio1; |
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gpio2 = &gpio2; |
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gpio3 = &gpio3; |
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gpio4 = &gpio4; |
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gpio5 = &gpio5; |
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gpio6 = &gpio6; |
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gpio7 = &gpio7; |
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gpio8 = &gpio8; |
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gpio9 = &gpio9; |
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serial0 = &uart1; |
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serial1 = &uart2; |
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serial2 = &uart3; |
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serial3 = &uart4; |
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serial4 = &uart5; |
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serial5 = &uart6; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu@0 { |
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compatible = "mti,mips14KEc"; |
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device_type = "cpu"; |
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}; |
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}; |
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soc { |
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compatible = "microchip,pic32mzda-infra"; |
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interrupts = <0 IRQ_TYPE_EDGE_RISING>; |
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}; |
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/* external clock input on TxCLKI pin */ |
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txcki: txcki_clk { |
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#clock-cells = <0>; |
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compatible = "fixed-clock"; |
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clock-frequency = <4000000>; |
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status = "disabled"; |
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}; |
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/* external input on REFCLKIx pin */ |
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refix: refix_clk { |
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#clock-cells = <0>; |
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compatible = "fixed-clock"; |
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clock-frequency = <24000000>; |
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status = "disabled"; |
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}; |
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rootclk: clock-controller@1f801200 { |
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compatible = "microchip,pic32mzda-clk"; |
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reg = <0x1f801200 0x200>; |
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#clock-cells = <1>; |
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microchip,pic32mzda-sosc; |
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}; |
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evic: interrupt-controller@1f810000 { |
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compatible = "microchip,pic32mzda-evic"; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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reg = <0x1f810000 0x1000>; |
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microchip,external-irqs = <3 8 13 18 23>; |
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}; |
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pic32_pinctrl: pinctrl@1f801400{ |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "microchip,pic32mzda-pinctrl"; |
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reg = <0x1f801400 0x400>; |
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clocks = <&rootclk PB1CLK>; |
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}; |
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/* PORTA */ |
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gpio0: gpio0@1f860000 { |
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compatible = "microchip,pic32mzda-gpio"; |
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reg = <0x1f860000 0x100>; |
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interrupts = <118 IRQ_TYPE_LEVEL_HIGH>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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clocks = <&rootclk PB4CLK>; |
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microchip,gpio-bank = <0>; |
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gpio-ranges = <&pic32_pinctrl 0 0 16>; |
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}; |
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/* PORTB */ |
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gpio1: gpio1@1f860100 { |
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compatible = "microchip,pic32mzda-gpio"; |
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reg = <0x1f860100 0x100>; |
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interrupts = <119 IRQ_TYPE_LEVEL_HIGH>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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clocks = <&rootclk PB4CLK>; |
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microchip,gpio-bank = <1>; |
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gpio-ranges = <&pic32_pinctrl 0 16 16>; |
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}; |
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/* PORTC */ |
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gpio2: gpio2@1f860200 { |
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compatible = "microchip,pic32mzda-gpio"; |
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reg = <0x1f860200 0x100>; |
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interrupts = <120 IRQ_TYPE_LEVEL_HIGH>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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clocks = <&rootclk PB4CLK>; |
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microchip,gpio-bank = <2>; |
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gpio-ranges = <&pic32_pinctrl 0 32 16>; |
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}; |
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/* PORTD */ |
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gpio3: gpio3@1f860300 { |
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compatible = "microchip,pic32mzda-gpio"; |
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reg = <0x1f860300 0x100>; |
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interrupts = <121 IRQ_TYPE_LEVEL_HIGH>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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clocks = <&rootclk PB4CLK>; |
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microchip,gpio-bank = <3>; |
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gpio-ranges = <&pic32_pinctrl 0 48 16>; |
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}; |
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/* PORTE */ |
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gpio4: gpio4@1f860400 { |
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compatible = "microchip,pic32mzda-gpio"; |
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reg = <0x1f860400 0x100>; |
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interrupts = <122 IRQ_TYPE_LEVEL_HIGH>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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clocks = <&rootclk PB4CLK>; |
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microchip,gpio-bank = <4>; |
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gpio-ranges = <&pic32_pinctrl 0 64 16>; |
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}; |
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/* PORTF */ |
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gpio5: gpio5@1f860500 { |
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compatible = "microchip,pic32mzda-gpio"; |
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reg = <0x1f860500 0x100>; |
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interrupts = <123 IRQ_TYPE_LEVEL_HIGH>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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clocks = <&rootclk PB4CLK>; |
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microchip,gpio-bank = <5>; |
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gpio-ranges = <&pic32_pinctrl 0 80 16>; |
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}; |
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/* PORTG */ |
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gpio6: gpio6@1f860600 { |
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compatible = "microchip,pic32mzda-gpio"; |
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reg = <0x1f860600 0x100>; |
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interrupts = <124 IRQ_TYPE_LEVEL_HIGH>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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clocks = <&rootclk PB4CLK>; |
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microchip,gpio-bank = <6>; |
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gpio-ranges = <&pic32_pinctrl 0 96 16>; |
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}; |
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/* PORTH */ |
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gpio7: gpio7@1f860700 { |
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compatible = "microchip,pic32mzda-gpio"; |
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reg = <0x1f860700 0x100>; |
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interrupts = <125 IRQ_TYPE_LEVEL_HIGH>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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clocks = <&rootclk PB4CLK>; |
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microchip,gpio-bank = <7>; |
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gpio-ranges = <&pic32_pinctrl 0 112 16>; |
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}; |
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/* PORTI does not exist */ |
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/* PORTJ */ |
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gpio8: gpio8@1f860800 { |
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compatible = "microchip,pic32mzda-gpio"; |
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reg = <0x1f860800 0x100>; |
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interrupts = <126 IRQ_TYPE_LEVEL_HIGH>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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clocks = <&rootclk PB4CLK>; |
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microchip,gpio-bank = <8>; |
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gpio-ranges = <&pic32_pinctrl 0 128 16>; |
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}; |
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/* PORTK */ |
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gpio9: gpio9@1f860900 { |
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compatible = "microchip,pic32mzda-gpio"; |
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reg = <0x1f860900 0x100>; |
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interrupts = <127 IRQ_TYPE_LEVEL_HIGH>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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clocks = <&rootclk PB4CLK>; |
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microchip,gpio-bank = <9>; |
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gpio-ranges = <&pic32_pinctrl 0 144 16>; |
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}; |
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sdhci: sdhci@1f8ec000 { |
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compatible = "microchip,pic32mzda-sdhci"; |
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reg = <0x1f8ec000 0x100>; |
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interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>; |
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clock-names = "base_clk", "sys_clk"; |
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bus-width = <4>; |
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cap-sd-highspeed; |
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status = "disabled"; |
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}; |
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uart1: serial@1f822000 { |
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compatible = "microchip,pic32mzda-uart"; |
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reg = <0x1f822000 0x50>; |
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interrupts = <112 IRQ_TYPE_LEVEL_HIGH>, |
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<113 IRQ_TYPE_LEVEL_HIGH>, |
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<114 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&rootclk PB2CLK>; |
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status = "disabled"; |
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}; |
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uart2: serial@1f822200 { |
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compatible = "microchip,pic32mzda-uart"; |
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reg = <0x1f822200 0x50>; |
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interrupts = <145 IRQ_TYPE_LEVEL_HIGH>, |
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<146 IRQ_TYPE_LEVEL_HIGH>, |
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<147 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&rootclk PB2CLK>; |
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status = "disabled"; |
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}; |
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uart3: serial@1f822400 { |
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compatible = "microchip,pic32mzda-uart"; |
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reg = <0x1f822400 0x50>; |
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interrupts = <157 IRQ_TYPE_LEVEL_HIGH>, |
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<158 IRQ_TYPE_LEVEL_HIGH>, |
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<159 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&rootclk PB2CLK>; |
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status = "disabled"; |
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}; |
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uart4: serial@1f822600 { |
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compatible = "microchip,pic32mzda-uart"; |
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reg = <0x1f822600 0x50>; |
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interrupts = <170 IRQ_TYPE_LEVEL_HIGH>, |
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<171 IRQ_TYPE_LEVEL_HIGH>, |
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<172 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&rootclk PB2CLK>; |
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status = "disabled"; |
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}; |
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uart5: serial@1f822800 { |
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compatible = "microchip,pic32mzda-uart"; |
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reg = <0x1f822800 0x50>; |
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interrupts = <179 IRQ_TYPE_LEVEL_HIGH>, |
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<180 IRQ_TYPE_LEVEL_HIGH>, |
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<181 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&rootclk PB2CLK>; |
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status = "disabled"; |
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}; |
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uart6: serial@1f822A00 { |
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compatible = "microchip,pic32mzda-uart"; |
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reg = <0x1f822A00 0x50>; |
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interrupts = <188 IRQ_TYPE_LEVEL_HIGH>, |
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<189 IRQ_TYPE_LEVEL_HIGH>, |
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<190 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&rootclk PB2CLK>; |
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status = "disabled"; |
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}; |
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};
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