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1038 lines
26 KiB
1038 lines
26 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT. |
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* |
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* Copyright (C) 2018-2020 Xilinx Inc. |
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* |
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* Author: Anurag Kumar Vulisha <[email protected]> |
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* Author: Subbaraya Sundeep <[email protected]> |
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* Author: Laurent Pinchart <[email protected]> |
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* |
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* This driver is tested for USB, SATA and Display Port currently. |
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* Other controllers PCIe and SGMII should also work but that is |
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* experimental as of now. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <dt-bindings/phy/phy.h> |
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/* |
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* Lane Registers |
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*/ |
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/* TX De-emphasis parameters */ |
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#define L0_TX_ANA_TM_18 0x0048 |
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#define L0_TX_ANA_TM_118 0x01d8 |
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#define L0_TX_ANA_TM_118_FORCE_17_0 BIT(0) |
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/* DN Resistor calibration code parameters */ |
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#define L0_TXPMA_ST_3 0x0b0c |
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#define L0_DN_CALIB_CODE 0x3f |
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/* PMA control parameters */ |
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#define L0_TXPMD_TM_45 0x0cb4 |
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#define L0_TXPMD_TM_48 0x0cc0 |
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#define L0_TXPMD_TM_45_OVER_DP_MAIN BIT(0) |
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#define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1) |
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#define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2) |
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#define L0_TXPMD_TM_45_ENABLE_DP_POST1 BIT(3) |
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#define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4) |
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#define L0_TXPMD_TM_45_ENABLE_DP_POST2 BIT(5) |
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/* PCS control parameters */ |
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#define L0_TM_DIG_6 0x106c |
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#define L0_TM_DIS_DESCRAMBLE_DECODER 0x0f |
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#define L0_TX_DIG_61 0x00f4 |
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#define L0_TM_DISABLE_SCRAMBLE_ENCODER 0x0f |
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/* PLL Test Mode register parameters */ |
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#define L0_TM_PLL_DIG_37 0x2094 |
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#define L0_TM_COARSE_CODE_LIMIT 0x10 |
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/* PLL SSC step size offsets */ |
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#define L0_PLL_SS_STEPS_0_LSB 0x2368 |
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#define L0_PLL_SS_STEPS_1_MSB 0x236c |
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#define L0_PLL_SS_STEP_SIZE_0_LSB 0x2370 |
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#define L0_PLL_SS_STEP_SIZE_1 0x2374 |
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#define L0_PLL_SS_STEP_SIZE_2 0x2378 |
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#define L0_PLL_SS_STEP_SIZE_3_MSB 0x237c |
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#define L0_PLL_STATUS_READ_1 0x23e4 |
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/* SSC step size parameters */ |
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#define STEP_SIZE_0_MASK 0xff |
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#define STEP_SIZE_1_MASK 0xff |
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#define STEP_SIZE_2_MASK 0xff |
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#define STEP_SIZE_3_MASK 0x3 |
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#define STEP_SIZE_SHIFT 8 |
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#define FORCE_STEP_SIZE 0x10 |
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#define FORCE_STEPS 0x20 |
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#define STEPS_0_MASK 0xff |
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#define STEPS_1_MASK 0x07 |
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/* Reference clock selection parameters */ |
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#define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4) |
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#define L0_REF_CLK_SEL_MASK 0x8f |
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/* Calibration digital logic parameters */ |
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#define L3_TM_CALIB_DIG19 0xec4c |
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#define L3_CALIB_DONE_STATUS 0xef14 |
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#define L3_TM_CALIB_DIG18 0xec48 |
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#define L3_TM_CALIB_DIG19_NSW 0x07 |
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#define L3_TM_CALIB_DIG18_NSW 0xe0 |
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#define L3_TM_OVERRIDE_NSW_CODE 0x20 |
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#define L3_CALIB_DONE 0x02 |
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#define L3_NSW_SHIFT 5 |
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#define L3_NSW_PIPE_SHIFT 4 |
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#define L3_NSW_CALIB_SHIFT 3 |
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#define PHY_REG_OFFSET 0x4000 |
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/* |
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* Global Registers |
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*/ |
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/* Refclk selection parameters */ |
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#define PLL_REF_SEL(n) (0x10000 + (n) * 4) |
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#define PLL_FREQ_MASK 0x1f |
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#define PLL_STATUS_LOCKED 0x10 |
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/* Inter Connect Matrix parameters */ |
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#define ICM_CFG0 0x10010 |
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#define ICM_CFG1 0x10014 |
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#define ICM_CFG0_L0_MASK 0x07 |
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#define ICM_CFG0_L1_MASK 0x70 |
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#define ICM_CFG1_L2_MASK 0x07 |
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#define ICM_CFG2_L3_MASK 0x70 |
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#define ICM_CFG_SHIFT 4 |
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/* Inter Connect Matrix allowed protocols */ |
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#define ICM_PROTOCOL_PD 0x0 |
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#define ICM_PROTOCOL_PCIE 0x1 |
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#define ICM_PROTOCOL_SATA 0x2 |
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#define ICM_PROTOCOL_USB 0x3 |
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#define ICM_PROTOCOL_DP 0x4 |
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#define ICM_PROTOCOL_SGMII 0x5 |
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/* Test Mode common reset control parameters */ |
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#define TM_CMN_RST 0x10018 |
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#define TM_CMN_RST_EN 0x1 |
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#define TM_CMN_RST_SET 0x2 |
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#define TM_CMN_RST_MASK 0x3 |
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/* Bus width parameters */ |
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#define TX_PROT_BUS_WIDTH 0x10040 |
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#define RX_PROT_BUS_WIDTH 0x10044 |
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#define PROT_BUS_WIDTH_10 0x0 |
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#define PROT_BUS_WIDTH_20 0x1 |
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#define PROT_BUS_WIDTH_40 0x2 |
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#define PROT_BUS_WIDTH_SHIFT(n) ((n) * 2) |
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#define PROT_BUS_WIDTH_MASK(n) GENMASK((n) * 2 + 1, (n) * 2) |
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/* Number of GT lanes */ |
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#define NUM_LANES 4 |
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/* SIOU SATA control register */ |
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#define SATA_CONTROL_OFFSET 0x0100 |
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/* Total number of controllers */ |
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#define CONTROLLERS_PER_LANE 5 |
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/* Protocol Type parameters */ |
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#define XPSGTR_TYPE_USB0 0 /* USB controller 0 */ |
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#define XPSGTR_TYPE_USB1 1 /* USB controller 1 */ |
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#define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */ |
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#define XPSGTR_TYPE_SATA_1 3 /* SATA controller lane 1 */ |
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#define XPSGTR_TYPE_PCIE_0 4 /* PCIe controller lane 0 */ |
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#define XPSGTR_TYPE_PCIE_1 5 /* PCIe controller lane 1 */ |
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#define XPSGTR_TYPE_PCIE_2 6 /* PCIe controller lane 2 */ |
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#define XPSGTR_TYPE_PCIE_3 7 /* PCIe controller lane 3 */ |
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#define XPSGTR_TYPE_DP_0 8 /* Display Port controller lane 0 */ |
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#define XPSGTR_TYPE_DP_1 9 /* Display Port controller lane 1 */ |
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#define XPSGTR_TYPE_SGMII0 10 /* Ethernet SGMII controller 0 */ |
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#define XPSGTR_TYPE_SGMII1 11 /* Ethernet SGMII controller 1 */ |
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#define XPSGTR_TYPE_SGMII2 12 /* Ethernet SGMII controller 2 */ |
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#define XPSGTR_TYPE_SGMII3 13 /* Ethernet SGMII controller 3 */ |
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/* Timeout values */ |
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#define TIMEOUT_US 1000 |
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struct xpsgtr_dev; |
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/** |
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* struct xpsgtr_ssc - structure to hold SSC settings for a lane |
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* @refclk_rate: PLL reference clock frequency |
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* @pll_ref_clk: value to be written to register for corresponding ref clk rate |
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* @steps: number of steps of SSC (Spread Spectrum Clock) |
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* @step_size: step size of each step |
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*/ |
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struct xpsgtr_ssc { |
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u32 refclk_rate; |
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u8 pll_ref_clk; |
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u32 steps; |
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u32 step_size; |
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}; |
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/** |
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* struct xpsgtr_phy - representation of a lane |
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* @phy: pointer to the kernel PHY device |
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* @type: controller which uses this lane |
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* @lane: lane number |
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* @protocol: protocol in which the lane operates |
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* @skip_phy_init: skip phy_init() if true |
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* @dev: pointer to the xpsgtr_dev instance |
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* @refclk: reference clock index |
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*/ |
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struct xpsgtr_phy { |
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struct phy *phy; |
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u8 type; |
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u8 lane; |
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u8 protocol; |
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bool skip_phy_init; |
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struct xpsgtr_dev *dev; |
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unsigned int refclk; |
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}; |
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/** |
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* struct xpsgtr_dev - representation of a ZynMP GT device |
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* @dev: pointer to device |
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* @serdes: serdes base address |
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* @siou: siou base address |
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* @gtr_mutex: mutex for locking |
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* @phys: PHY lanes |
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* @refclk_sscs: spread spectrum settings for the reference clocks |
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* @clk: reference clocks |
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* @tx_term_fix: fix for GT issue |
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* @saved_icm_cfg0: stored value of ICM CFG0 register |
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* @saved_icm_cfg1: stored value of ICM CFG1 register |
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*/ |
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struct xpsgtr_dev { |
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struct device *dev; |
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void __iomem *serdes; |
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void __iomem *siou; |
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struct mutex gtr_mutex; /* mutex for locking */ |
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struct xpsgtr_phy phys[NUM_LANES]; |
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const struct xpsgtr_ssc *refclk_sscs[NUM_LANES]; |
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struct clk *clk[NUM_LANES]; |
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bool tx_term_fix; |
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unsigned int saved_icm_cfg0; |
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unsigned int saved_icm_cfg1; |
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}; |
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/* |
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* Configuration Data |
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*/ |
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/* lookup table to hold all settings needed for a ref clock frequency */ |
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static const struct xpsgtr_ssc ssc_lookup[] = { |
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{ 19200000, 0x05, 608, 264020 }, |
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{ 20000000, 0x06, 634, 243454 }, |
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{ 24000000, 0x07, 760, 168973 }, |
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{ 26000000, 0x08, 824, 143860 }, |
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{ 27000000, 0x09, 856, 86551 }, |
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{ 38400000, 0x0a, 1218, 65896 }, |
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{ 40000000, 0x0b, 634, 243454 }, |
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{ 52000000, 0x0c, 824, 143860 }, |
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{ 100000000, 0x0d, 1058, 87533 }, |
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{ 108000000, 0x0e, 856, 86551 }, |
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{ 125000000, 0x0f, 992, 119497 }, |
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{ 135000000, 0x10, 1070, 55393 }, |
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{ 150000000, 0x11, 792, 187091 } |
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}; |
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/* |
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* I/O Accessors |
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*/ |
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static inline u32 xpsgtr_read(struct xpsgtr_dev *gtr_dev, u32 reg) |
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{ |
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return readl(gtr_dev->serdes + reg); |
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} |
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static inline void xpsgtr_write(struct xpsgtr_dev *gtr_dev, u32 reg, u32 value) |
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{ |
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writel(value, gtr_dev->serdes + reg); |
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} |
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static inline void xpsgtr_clr_set(struct xpsgtr_dev *gtr_dev, u32 reg, |
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u32 clr, u32 set) |
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{ |
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u32 value = xpsgtr_read(gtr_dev, reg); |
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value &= ~clr; |
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value |= set; |
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xpsgtr_write(gtr_dev, reg, value); |
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} |
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static inline u32 xpsgtr_read_phy(struct xpsgtr_phy *gtr_phy, u32 reg) |
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{ |
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void __iomem *addr = gtr_phy->dev->serdes |
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+ gtr_phy->lane * PHY_REG_OFFSET + reg; |
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return readl(addr); |
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} |
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static inline void xpsgtr_write_phy(struct xpsgtr_phy *gtr_phy, |
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u32 reg, u32 value) |
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{ |
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void __iomem *addr = gtr_phy->dev->serdes |
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+ gtr_phy->lane * PHY_REG_OFFSET + reg; |
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writel(value, addr); |
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} |
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static inline void xpsgtr_clr_set_phy(struct xpsgtr_phy *gtr_phy, |
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u32 reg, u32 clr, u32 set) |
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{ |
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void __iomem *addr = gtr_phy->dev->serdes |
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+ gtr_phy->lane * PHY_REG_OFFSET + reg; |
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writel((readl(addr) & ~clr) | set, addr); |
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} |
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/* |
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* Hardware Configuration |
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*/ |
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/* Wait for the PLL to lock (with a timeout). */ |
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static int xpsgtr_wait_pll_lock(struct phy *phy) |
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{ |
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struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy); |
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struct xpsgtr_dev *gtr_dev = gtr_phy->dev; |
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unsigned int timeout = TIMEOUT_US; |
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int ret; |
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dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n"); |
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while (1) { |
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u32 reg = xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1); |
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if ((reg & PLL_STATUS_LOCKED) == PLL_STATUS_LOCKED) { |
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ret = 0; |
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break; |
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} |
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if (--timeout == 0) { |
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ret = -ETIMEDOUT; |
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break; |
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} |
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udelay(1); |
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} |
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if (ret == -ETIMEDOUT) |
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dev_err(gtr_dev->dev, |
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"lane %u (type %u, protocol %u): PLL lock timeout\n", |
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gtr_phy->lane, gtr_phy->type, gtr_phy->protocol); |
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return ret; |
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} |
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/* Configure PLL and spread-sprectrum clock. */ |
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static void xpsgtr_configure_pll(struct xpsgtr_phy *gtr_phy) |
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{ |
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const struct xpsgtr_ssc *ssc; |
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u32 step_size; |
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ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk]; |
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step_size = ssc->step_size; |
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xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane), |
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PLL_FREQ_MASK, ssc->pll_ref_clk); |
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/* Enable lane clock sharing, if required */ |
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if (gtr_phy->refclk != gtr_phy->lane) { |
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/* Lane3 Ref Clock Selection Register */ |
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xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), |
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L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk); |
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} |
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/* SSC step size [7:0] */ |
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xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_0_LSB, |
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STEP_SIZE_0_MASK, step_size & STEP_SIZE_0_MASK); |
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/* SSC step size [15:8] */ |
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step_size >>= STEP_SIZE_SHIFT; |
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xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_1, |
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STEP_SIZE_1_MASK, step_size & STEP_SIZE_1_MASK); |
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/* SSC step size [23:16] */ |
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step_size >>= STEP_SIZE_SHIFT; |
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xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_2, |
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STEP_SIZE_2_MASK, step_size & STEP_SIZE_2_MASK); |
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/* SSC steps [7:0] */ |
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xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_0_LSB, |
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STEPS_0_MASK, ssc->steps & STEPS_0_MASK); |
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/* SSC steps [10:8] */ |
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xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_1_MSB, |
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STEPS_1_MASK, |
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(ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK); |
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/* SSC step size [24:25] */ |
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step_size >>= STEP_SIZE_SHIFT; |
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xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_3_MSB, |
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STEP_SIZE_3_MASK, (step_size & STEP_SIZE_3_MASK) | |
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FORCE_STEP_SIZE | FORCE_STEPS); |
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} |
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/* Configure the lane protocol. */ |
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static void xpsgtr_lane_set_protocol(struct xpsgtr_phy *gtr_phy) |
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{ |
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struct xpsgtr_dev *gtr_dev = gtr_phy->dev; |
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u8 protocol = gtr_phy->protocol; |
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switch (gtr_phy->lane) { |
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case 0: |
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xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L0_MASK, protocol); |
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break; |
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case 1: |
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xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L1_MASK, |
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protocol << ICM_CFG_SHIFT); |
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break; |
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case 2: |
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xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L0_MASK, protocol); |
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break; |
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case 3: |
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xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L1_MASK, |
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protocol << ICM_CFG_SHIFT); |
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break; |
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default: |
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/* We already checked 0 <= lane <= 3 */ |
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break; |
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} |
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} |
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/* Bypass (de)scrambler and 8b/10b decoder and encoder. */ |
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static void xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy *gtr_phy) |
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{ |
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xpsgtr_write_phy(gtr_phy, L0_TM_DIG_6, L0_TM_DIS_DESCRAMBLE_DECODER); |
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xpsgtr_write_phy(gtr_phy, L0_TX_DIG_61, L0_TM_DISABLE_SCRAMBLE_ENCODER); |
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} |
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/* DP-specific initialization. */ |
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static void xpsgtr_phy_init_dp(struct xpsgtr_phy *gtr_phy) |
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{ |
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xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_45, |
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L0_TXPMD_TM_45_OVER_DP_MAIN | |
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L0_TXPMD_TM_45_ENABLE_DP_MAIN | |
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L0_TXPMD_TM_45_OVER_DP_POST1 | |
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L0_TXPMD_TM_45_OVER_DP_POST2 | |
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L0_TXPMD_TM_45_ENABLE_DP_POST2); |
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xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_118, |
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L0_TX_ANA_TM_118_FORCE_17_0); |
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} |
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/* SATA-specific initialization. */ |
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static void xpsgtr_phy_init_sata(struct xpsgtr_phy *gtr_phy) |
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{ |
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struct xpsgtr_dev *gtr_dev = gtr_phy->dev; |
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xpsgtr_bypass_scrambler_8b10b(gtr_phy); |
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writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET); |
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} |
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/* SGMII-specific initialization. */ |
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static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy) |
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{ |
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struct xpsgtr_dev *gtr_dev = gtr_phy->dev; |
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u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane); |
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u32 val = PROT_BUS_WIDTH_10 << PROT_BUS_WIDTH_SHIFT(gtr_phy->lane); |
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/* Set SGMII protocol TX and RX bus width to 10 bits. */ |
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xpsgtr_clr_set(gtr_dev, TX_PROT_BUS_WIDTH, mask, val); |
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xpsgtr_clr_set(gtr_dev, RX_PROT_BUS_WIDTH, mask, val); |
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xpsgtr_bypass_scrambler_8b10b(gtr_phy); |
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} |
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/* Configure TX de-emphasis and margining for DP. */ |
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static void xpsgtr_phy_configure_dp(struct xpsgtr_phy *gtr_phy, unsigned int pre, |
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unsigned int voltage) |
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{ |
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static const u8 voltage_swing[4][4] = { |
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{ 0x2a, 0x27, 0x24, 0x20 }, |
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{ 0x27, 0x23, 0x20, 0xff }, |
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{ 0x24, 0x20, 0xff, 0xff }, |
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{ 0xff, 0xff, 0xff, 0xff } |
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}; |
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static const u8 pre_emphasis[4][4] = { |
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{ 0x02, 0x02, 0x02, 0x02 }, |
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{ 0x01, 0x01, 0x01, 0xff }, |
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{ 0x00, 0x00, 0xff, 0xff }, |
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{ 0xff, 0xff, 0xff, 0xff } |
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}; |
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xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_48, voltage_swing[pre][voltage]); |
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xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_18, pre_emphasis[pre][voltage]); |
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} |
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/* |
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* PHY Operations |
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*/ |
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static bool xpsgtr_phy_init_required(struct xpsgtr_phy *gtr_phy) |
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{ |
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/* |
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* As USB may save the snapshot of the states during hibernation, doing |
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* phy_init() will put the USB controller into reset, resulting in the |
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* losing of the saved snapshot. So try to avoid phy_init() for USB |
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* except when gtr_phy->skip_phy_init is false (this happens when FPD is |
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* shutdown during suspend or when gt lane is changed from current one) |
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*/ |
|
if (gtr_phy->protocol == ICM_PROTOCOL_USB && gtr_phy->skip_phy_init) |
|
return false; |
|
else |
|
return true; |
|
} |
|
|
|
/* |
|
* There is a functional issue in the GT. The TX termination resistance can be |
|
* out of spec due to a issue in the calibration logic. This is the workaround |
|
* to fix it, required for XCZU9EG silicon. |
|
*/ |
|
static int xpsgtr_phy_tx_term_fix(struct xpsgtr_phy *gtr_phy) |
|
{ |
|
struct xpsgtr_dev *gtr_dev = gtr_phy->dev; |
|
u32 timeout = TIMEOUT_US; |
|
u32 nsw; |
|
|
|
/* Enabling Test Mode control for CMN Rest */ |
|
xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET); |
|
|
|
/* Set Test Mode reset */ |
|
xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN); |
|
|
|
xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18, 0x00); |
|
xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, L3_TM_OVERRIDE_NSW_CODE); |
|
|
|
/* |
|
* As a part of work around sequence for PMOS calibration fix, |
|
* we need to configure any lane ICM_CFG to valid protocol. This |
|
* will deassert the CMN_Resetn signal. |
|
*/ |
|
xpsgtr_lane_set_protocol(gtr_phy); |
|
|
|
/* Clear Test Mode reset */ |
|
xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET); |
|
|
|
dev_dbg(gtr_dev->dev, "calibrating...\n"); |
|
|
|
do { |
|
u32 reg = xpsgtr_read(gtr_dev, L3_CALIB_DONE_STATUS); |
|
|
|
if ((reg & L3_CALIB_DONE) == L3_CALIB_DONE) |
|
break; |
|
|
|
if (!--timeout) { |
|
dev_err(gtr_dev->dev, "calibration time out\n"); |
|
return -ETIMEDOUT; |
|
} |
|
|
|
udelay(1); |
|
} while (timeout > 0); |
|
|
|
dev_dbg(gtr_dev->dev, "calibration done\n"); |
|
|
|
/* Reading NMOS Register Code */ |
|
nsw = xpsgtr_read(gtr_dev, L0_TXPMA_ST_3) & L0_DN_CALIB_CODE; |
|
|
|
/* Set Test Mode reset */ |
|
xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN); |
|
|
|
/* Writing NMOS register values back [5:3] */ |
|
xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, nsw >> L3_NSW_CALIB_SHIFT); |
|
|
|
/* Writing NMOS register value [2:0] */ |
|
xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18, |
|
((nsw & L3_TM_CALIB_DIG19_NSW) << L3_NSW_SHIFT) | |
|
(1 << L3_NSW_PIPE_SHIFT)); |
|
|
|
/* Clear Test Mode reset */ |
|
xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET); |
|
|
|
return 0; |
|
} |
|
|
|
static int xpsgtr_phy_init(struct phy *phy) |
|
{ |
|
struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy); |
|
struct xpsgtr_dev *gtr_dev = gtr_phy->dev; |
|
int ret = 0; |
|
|
|
mutex_lock(>r_dev->gtr_mutex); |
|
|
|
/* Skip initialization if not required. */ |
|
if (!xpsgtr_phy_init_required(gtr_phy)) |
|
goto out; |
|
|
|
if (gtr_dev->tx_term_fix) { |
|
ret = xpsgtr_phy_tx_term_fix(gtr_phy); |
|
if (ret < 0) |
|
goto out; |
|
|
|
gtr_dev->tx_term_fix = false; |
|
} |
|
|
|
/* Enable coarse code saturation limiting logic. */ |
|
xpsgtr_write_phy(gtr_phy, L0_TM_PLL_DIG_37, L0_TM_COARSE_CODE_LIMIT); |
|
|
|
/* |
|
* Configure the PLL, the lane protocol, and perform protocol-specific |
|
* initialization. |
|
*/ |
|
xpsgtr_configure_pll(gtr_phy); |
|
xpsgtr_lane_set_protocol(gtr_phy); |
|
|
|
switch (gtr_phy->protocol) { |
|
case ICM_PROTOCOL_DP: |
|
xpsgtr_phy_init_dp(gtr_phy); |
|
break; |
|
|
|
case ICM_PROTOCOL_SATA: |
|
xpsgtr_phy_init_sata(gtr_phy); |
|
break; |
|
|
|
case ICM_PROTOCOL_SGMII: |
|
xpsgtr_phy_init_sgmii(gtr_phy); |
|
break; |
|
} |
|
|
|
out: |
|
mutex_unlock(>r_dev->gtr_mutex); |
|
return ret; |
|
} |
|
|
|
static int xpsgtr_phy_exit(struct phy *phy) |
|
{ |
|
struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy); |
|
|
|
gtr_phy->skip_phy_init = false; |
|
|
|
return 0; |
|
} |
|
|
|
static int xpsgtr_phy_power_on(struct phy *phy) |
|
{ |
|
struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy); |
|
int ret = 0; |
|
|
|
/* Skip initialization if not required. */ |
|
if (!xpsgtr_phy_init_required(gtr_phy)) |
|
return ret; |
|
/* |
|
* Wait for the PLL to lock. For DP, only wait on DP0 to avoid |
|
* cumulating waits for both lanes. The user is expected to initialize |
|
* lane 0 last. |
|
*/ |
|
if (gtr_phy->protocol != ICM_PROTOCOL_DP || |
|
gtr_phy->type == XPSGTR_TYPE_DP_0) |
|
ret = xpsgtr_wait_pll_lock(phy); |
|
|
|
return ret; |
|
} |
|
|
|
static int xpsgtr_phy_configure(struct phy *phy, union phy_configure_opts *opts) |
|
{ |
|
struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy); |
|
|
|
if (gtr_phy->protocol != ICM_PROTOCOL_DP) |
|
return 0; |
|
|
|
xpsgtr_phy_configure_dp(gtr_phy, opts->dp.pre[0], opts->dp.voltage[0]); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct phy_ops xpsgtr_phyops = { |
|
.init = xpsgtr_phy_init, |
|
.exit = xpsgtr_phy_exit, |
|
.power_on = xpsgtr_phy_power_on, |
|
.configure = xpsgtr_phy_configure, |
|
.owner = THIS_MODULE, |
|
}; |
|
|
|
/* |
|
* OF Xlate Support |
|
*/ |
|
|
|
/* Set the lane type and protocol based on the PHY type and instance number. */ |
|
static int xpsgtr_set_lane_type(struct xpsgtr_phy *gtr_phy, u8 phy_type, |
|
unsigned int phy_instance) |
|
{ |
|
unsigned int num_phy_types; |
|
const int *phy_types; |
|
|
|
switch (phy_type) { |
|
case PHY_TYPE_SATA: { |
|
static const int types[] = { |
|
XPSGTR_TYPE_SATA_0, |
|
XPSGTR_TYPE_SATA_1, |
|
}; |
|
|
|
phy_types = types; |
|
num_phy_types = ARRAY_SIZE(types); |
|
gtr_phy->protocol = ICM_PROTOCOL_SATA; |
|
break; |
|
} |
|
case PHY_TYPE_USB3: { |
|
static const int types[] = { |
|
XPSGTR_TYPE_USB0, |
|
XPSGTR_TYPE_USB1, |
|
}; |
|
|
|
phy_types = types; |
|
num_phy_types = ARRAY_SIZE(types); |
|
gtr_phy->protocol = ICM_PROTOCOL_USB; |
|
break; |
|
} |
|
case PHY_TYPE_DP: { |
|
static const int types[] = { |
|
XPSGTR_TYPE_DP_0, |
|
XPSGTR_TYPE_DP_1, |
|
}; |
|
|
|
phy_types = types; |
|
num_phy_types = ARRAY_SIZE(types); |
|
gtr_phy->protocol = ICM_PROTOCOL_DP; |
|
break; |
|
} |
|
case PHY_TYPE_PCIE: { |
|
static const int types[] = { |
|
XPSGTR_TYPE_PCIE_0, |
|
XPSGTR_TYPE_PCIE_1, |
|
XPSGTR_TYPE_PCIE_2, |
|
XPSGTR_TYPE_PCIE_3, |
|
}; |
|
|
|
phy_types = types; |
|
num_phy_types = ARRAY_SIZE(types); |
|
gtr_phy->protocol = ICM_PROTOCOL_PCIE; |
|
break; |
|
} |
|
case PHY_TYPE_SGMII: { |
|
static const int types[] = { |
|
XPSGTR_TYPE_SGMII0, |
|
XPSGTR_TYPE_SGMII1, |
|
XPSGTR_TYPE_SGMII2, |
|
XPSGTR_TYPE_SGMII3, |
|
}; |
|
|
|
phy_types = types; |
|
num_phy_types = ARRAY_SIZE(types); |
|
gtr_phy->protocol = ICM_PROTOCOL_SGMII; |
|
break; |
|
} |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
if (phy_instance >= num_phy_types) |
|
return -EINVAL; |
|
|
|
gtr_phy->type = phy_types[phy_instance]; |
|
return 0; |
|
} |
|
|
|
/* |
|
* Valid combinations of controllers and lanes (Interconnect Matrix). |
|
*/ |
|
static const unsigned int icm_matrix[NUM_LANES][CONTROLLERS_PER_LANE] = { |
|
{ XPSGTR_TYPE_PCIE_0, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0, |
|
XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII0 }, |
|
{ XPSGTR_TYPE_PCIE_1, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB0, |
|
XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII1 }, |
|
{ XPSGTR_TYPE_PCIE_2, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0, |
|
XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII2 }, |
|
{ XPSGTR_TYPE_PCIE_3, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB1, |
|
XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII3 } |
|
}; |
|
|
|
/* Translate OF phandle and args to PHY instance. */ |
|
static struct phy *xpsgtr_xlate(struct device *dev, |
|
struct of_phandle_args *args) |
|
{ |
|
struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev); |
|
struct xpsgtr_phy *gtr_phy; |
|
unsigned int phy_instance; |
|
unsigned int phy_lane; |
|
unsigned int phy_type; |
|
unsigned int refclk; |
|
unsigned int i; |
|
int ret; |
|
|
|
if (args->args_count != 4) { |
|
dev_err(dev, "Invalid number of cells in 'phy' property\n"); |
|
return ERR_PTR(-EINVAL); |
|
} |
|
|
|
/* |
|
* Get the PHY parameters from the OF arguments and derive the lane |
|
* type. |
|
*/ |
|
phy_lane = args->args[0]; |
|
if (phy_lane >= ARRAY_SIZE(gtr_dev->phys)) { |
|
dev_err(dev, "Invalid lane number %u\n", phy_lane); |
|
return ERR_PTR(-ENODEV); |
|
} |
|
|
|
gtr_phy = >r_dev->phys[phy_lane]; |
|
phy_type = args->args[1]; |
|
phy_instance = args->args[2]; |
|
|
|
ret = xpsgtr_set_lane_type(gtr_phy, phy_type, phy_instance); |
|
if (ret < 0) { |
|
dev_err(gtr_dev->dev, "Invalid PHY type and/or instance\n"); |
|
return ERR_PTR(ret); |
|
} |
|
|
|
refclk = args->args[3]; |
|
if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) || |
|
!gtr_dev->refclk_sscs[refclk]) { |
|
dev_err(dev, "Invalid reference clock number %u\n", refclk); |
|
return ERR_PTR(-EINVAL); |
|
} |
|
|
|
gtr_phy->refclk = refclk; |
|
|
|
/* |
|
* Ensure that the Interconnect Matrix is obeyed, i.e a given lane type |
|
* is allowed to operate on the lane. |
|
*/ |
|
for (i = 0; i < CONTROLLERS_PER_LANE; i++) { |
|
if (icm_matrix[phy_lane][i] == gtr_phy->type) |
|
return gtr_phy->phy; |
|
} |
|
|
|
return ERR_PTR(-EINVAL); |
|
} |
|
|
|
/* |
|
* Power Management |
|
*/ |
|
|
|
static int __maybe_unused xpsgtr_suspend(struct device *dev) |
|
{ |
|
struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev); |
|
unsigned int i; |
|
|
|
/* Save the snapshot ICM_CFG registers. */ |
|
gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0); |
|
gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1); |
|
|
|
for (i = 0; i < ARRAY_SIZE(gtr_dev->clk); i++) |
|
clk_disable_unprepare(gtr_dev->clk[i]); |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused xpsgtr_resume(struct device *dev) |
|
{ |
|
struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev); |
|
unsigned int icm_cfg0, icm_cfg1; |
|
unsigned int i; |
|
bool skip_phy_init; |
|
int err; |
|
|
|
for (i = 0; i < ARRAY_SIZE(gtr_dev->clk); i++) { |
|
err = clk_prepare_enable(gtr_dev->clk[i]); |
|
if (err) |
|
goto err_clk_put; |
|
} |
|
|
|
icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0); |
|
icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1); |
|
|
|
/* Return if no GT lanes got configured before suspend. */ |
|
if (!gtr_dev->saved_icm_cfg0 && !gtr_dev->saved_icm_cfg1) |
|
return 0; |
|
|
|
/* Check if the ICM configurations changed after suspend. */ |
|
if (icm_cfg0 == gtr_dev->saved_icm_cfg0 && |
|
icm_cfg1 == gtr_dev->saved_icm_cfg1) |
|
skip_phy_init = true; |
|
else |
|
skip_phy_init = false; |
|
|
|
/* Update the skip_phy_init for all gtr_phy instances. */ |
|
for (i = 0; i < ARRAY_SIZE(gtr_dev->phys); i++) |
|
gtr_dev->phys[i].skip_phy_init = skip_phy_init; |
|
|
|
return 0; |
|
|
|
err_clk_put: |
|
while (i--) |
|
clk_disable_unprepare(gtr_dev->clk[i]); |
|
|
|
return err; |
|
} |
|
|
|
static const struct dev_pm_ops xpsgtr_pm_ops = { |
|
SET_SYSTEM_SLEEP_PM_OPS(xpsgtr_suspend, xpsgtr_resume) |
|
}; |
|
|
|
/* |
|
* Probe & Platform Driver |
|
*/ |
|
|
|
static int xpsgtr_get_ref_clocks(struct xpsgtr_dev *gtr_dev) |
|
{ |
|
unsigned int refclk; |
|
int ret; |
|
|
|
for (refclk = 0; refclk < ARRAY_SIZE(gtr_dev->refclk_sscs); ++refclk) { |
|
unsigned long rate; |
|
unsigned int i; |
|
struct clk *clk; |
|
char name[8]; |
|
|
|
snprintf(name, sizeof(name), "ref%u", refclk); |
|
clk = devm_clk_get_optional(gtr_dev->dev, name); |
|
if (IS_ERR(clk)) { |
|
ret = dev_err_probe(gtr_dev->dev, PTR_ERR(clk), |
|
"Failed to get reference clock %u\n", |
|
refclk); |
|
goto err_clk_put; |
|
} |
|
|
|
if (!clk) |
|
continue; |
|
|
|
ret = clk_prepare_enable(clk); |
|
if (ret) |
|
goto err_clk_put; |
|
|
|
gtr_dev->clk[refclk] = clk; |
|
|
|
/* |
|
* Get the spread spectrum (SSC) settings for the reference |
|
* clock rate. |
|
*/ |
|
rate = clk_get_rate(clk); |
|
|
|
for (i = 0 ; i < ARRAY_SIZE(ssc_lookup); i++) { |
|
if (rate == ssc_lookup[i].refclk_rate) { |
|
gtr_dev->refclk_sscs[refclk] = &ssc_lookup[i]; |
|
break; |
|
} |
|
} |
|
|
|
if (i == ARRAY_SIZE(ssc_lookup)) { |
|
dev_err(gtr_dev->dev, |
|
"Invalid rate %lu for reference clock %u\n", |
|
rate, refclk); |
|
ret = -EINVAL; |
|
goto err_clk_put; |
|
} |
|
} |
|
|
|
return 0; |
|
|
|
err_clk_put: |
|
while (refclk--) |
|
clk_disable_unprepare(gtr_dev->clk[refclk]); |
|
|
|
return ret; |
|
} |
|
|
|
static int xpsgtr_probe(struct platform_device *pdev) |
|
{ |
|
struct device_node *np = pdev->dev.of_node; |
|
struct xpsgtr_dev *gtr_dev; |
|
struct phy_provider *provider; |
|
unsigned int port; |
|
unsigned int i; |
|
int ret; |
|
|
|
gtr_dev = devm_kzalloc(&pdev->dev, sizeof(*gtr_dev), GFP_KERNEL); |
|
if (!gtr_dev) |
|
return -ENOMEM; |
|
|
|
gtr_dev->dev = &pdev->dev; |
|
platform_set_drvdata(pdev, gtr_dev); |
|
|
|
mutex_init(>r_dev->gtr_mutex); |
|
|
|
if (of_device_is_compatible(np, "xlnx,zynqmp-psgtr")) |
|
gtr_dev->tx_term_fix = |
|
of_property_read_bool(np, "xlnx,tx-termination-fix"); |
|
|
|
/* Acquire resources. */ |
|
gtr_dev->serdes = devm_platform_ioremap_resource_byname(pdev, "serdes"); |
|
if (IS_ERR(gtr_dev->serdes)) |
|
return PTR_ERR(gtr_dev->serdes); |
|
|
|
gtr_dev->siou = devm_platform_ioremap_resource_byname(pdev, "siou"); |
|
if (IS_ERR(gtr_dev->siou)) |
|
return PTR_ERR(gtr_dev->siou); |
|
|
|
ret = xpsgtr_get_ref_clocks(gtr_dev); |
|
if (ret) |
|
return ret; |
|
|
|
/* Create PHYs. */ |
|
for (port = 0; port < ARRAY_SIZE(gtr_dev->phys); ++port) { |
|
struct xpsgtr_phy *gtr_phy = >r_dev->phys[port]; |
|
struct phy *phy; |
|
|
|
gtr_phy->lane = port; |
|
gtr_phy->dev = gtr_dev; |
|
|
|
phy = devm_phy_create(&pdev->dev, np, &xpsgtr_phyops); |
|
if (IS_ERR(phy)) { |
|
dev_err(&pdev->dev, "failed to create PHY\n"); |
|
ret = PTR_ERR(phy); |
|
goto err_clk_put; |
|
} |
|
|
|
gtr_phy->phy = phy; |
|
phy_set_drvdata(phy, gtr_phy); |
|
} |
|
|
|
/* Register the PHY provider. */ |
|
provider = devm_of_phy_provider_register(&pdev->dev, xpsgtr_xlate); |
|
if (IS_ERR(provider)) { |
|
dev_err(&pdev->dev, "registering provider failed\n"); |
|
ret = PTR_ERR(provider); |
|
goto err_clk_put; |
|
} |
|
return 0; |
|
|
|
err_clk_put: |
|
for (i = 0; i < ARRAY_SIZE(gtr_dev->clk); i++) |
|
clk_disable_unprepare(gtr_dev->clk[i]); |
|
|
|
return ret; |
|
} |
|
|
|
static const struct of_device_id xpsgtr_of_match[] = { |
|
{ .compatible = "xlnx,zynqmp-psgtr", }, |
|
{ .compatible = "xlnx,zynqmp-psgtr-v1.1", }, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, xpsgtr_of_match); |
|
|
|
static struct platform_driver xpsgtr_driver = { |
|
.probe = xpsgtr_probe, |
|
.driver = { |
|
.name = "xilinx-psgtr", |
|
.of_match_table = xpsgtr_of_match, |
|
.pm = &xpsgtr_pm_ops, |
|
}, |
|
}; |
|
|
|
module_platform_driver(xpsgtr_driver); |
|
|
|
MODULE_AUTHOR("Xilinx Inc."); |
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_DESCRIPTION("Xilinx ZynqMP High speed Gigabit Transceiver");
|
|
|