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380 lines
10 KiB
380 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Driver for the CS5535/CS5536 Multi-Function General Purpose Timers (MFGPT) |
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* |
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* Copyright (C) 2006, Advanced Micro Devices, Inc. |
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* Copyright (C) 2007 Andres Salomon <[email protected]> |
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* Copyright (C) 2009 Andres Salomon <[email protected]> |
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* |
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* The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/spinlock.h> |
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#include <linux/interrupt.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/cs5535.h> |
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#include <linux/slab.h> |
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#define DRV_NAME "cs5535-mfgpt" |
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static int mfgpt_reset_timers; |
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module_param_named(mfgptfix, mfgpt_reset_timers, int, 0644); |
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MODULE_PARM_DESC(mfgptfix, "Try to reset the MFGPT timers during init; " |
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"required by some broken BIOSes (ie, TinyBIOS < 0.99) or kexec " |
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"(1 = reset the MFGPT using an undocumented bit, " |
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"2 = perform a soft reset by unconfiguring all timers); " |
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"use what works best for you."); |
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struct cs5535_mfgpt_timer { |
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struct cs5535_mfgpt_chip *chip; |
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int nr; |
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}; |
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static struct cs5535_mfgpt_chip { |
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DECLARE_BITMAP(avail, MFGPT_MAX_TIMERS); |
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resource_size_t base; |
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struct platform_device *pdev; |
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spinlock_t lock; |
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int initialized; |
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} cs5535_mfgpt_chip; |
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int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp, |
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int event, int enable) |
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{ |
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uint32_t msr, mask, value, dummy; |
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int shift = (cmp == MFGPT_CMP1) ? 0 : 8; |
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if (!timer) { |
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WARN_ON(1); |
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return -EIO; |
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} |
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/* |
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* The register maps for these are described in sections 6.17.1.x of |
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* the AMD Geode CS5536 Companion Device Data Book. |
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*/ |
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switch (event) { |
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case MFGPT_EVENT_RESET: |
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/* |
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* XXX: According to the docs, we cannot reset timers above |
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* 6; that is, resets for 7 and 8 will be ignored. Is this |
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* a problem? -dilinger |
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*/ |
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msr = MSR_MFGPT_NR; |
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mask = 1 << (timer->nr + 24); |
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break; |
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case MFGPT_EVENT_NMI: |
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msr = MSR_MFGPT_NR; |
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mask = 1 << (timer->nr + shift); |
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break; |
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case MFGPT_EVENT_IRQ: |
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msr = MSR_MFGPT_IRQ; |
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mask = 1 << (timer->nr + shift); |
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break; |
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default: |
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return -EIO; |
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} |
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rdmsr(msr, value, dummy); |
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if (enable) |
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value |= mask; |
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else |
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value &= ~mask; |
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wrmsr(msr, value, dummy); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(cs5535_mfgpt_toggle_event); |
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int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp, int *irq, |
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int enable) |
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{ |
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uint32_t zsel, lpc, dummy; |
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int shift; |
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if (!timer) { |
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WARN_ON(1); |
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return -EIO; |
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} |
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/* |
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* Unfortunately, MFGPTs come in pairs sharing their IRQ lines. If VSA |
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* is using the same CMP of the timer's Siamese twin, the IRQ is set to |
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* 2, and we mustn't use nor change it. |
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* XXX: Likewise, 2 Linux drivers might clash if the 2nd overwrites the |
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* IRQ of the 1st. This can only happen if forcing an IRQ, calling this |
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* with *irq==0 is safe. Currently there _are_ no 2 drivers. |
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*/ |
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rdmsr(MSR_PIC_ZSEL_LOW, zsel, dummy); |
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shift = ((cmp == MFGPT_CMP1 ? 0 : 4) + timer->nr % 4) * 4; |
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if (((zsel >> shift) & 0xF) == 2) |
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return -EIO; |
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/* Choose IRQ: if none supplied, keep IRQ already set or use default */ |
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if (!*irq) |
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*irq = (zsel >> shift) & 0xF; |
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if (!*irq) |
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*irq = CONFIG_CS5535_MFGPT_DEFAULT_IRQ; |
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/* Can't use IRQ if it's 0 (=disabled), 2, or routed to LPC */ |
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if (*irq < 1 || *irq == 2 || *irq > 15) |
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return -EIO; |
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rdmsr(MSR_PIC_IRQM_LPC, lpc, dummy); |
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if (lpc & (1 << *irq)) |
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return -EIO; |
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/* All chosen and checked - go for it */ |
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if (cs5535_mfgpt_toggle_event(timer, cmp, MFGPT_EVENT_IRQ, enable)) |
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return -EIO; |
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if (enable) { |
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zsel = (zsel & ~(0xF << shift)) | (*irq << shift); |
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wrmsr(MSR_PIC_ZSEL_LOW, zsel, dummy); |
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} |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(cs5535_mfgpt_set_irq); |
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struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer_nr, int domain) |
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{ |
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struct cs5535_mfgpt_chip *mfgpt = &cs5535_mfgpt_chip; |
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struct cs5535_mfgpt_timer *timer = NULL; |
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unsigned long flags; |
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int max; |
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if (!mfgpt->initialized) |
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goto done; |
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/* only allocate timers from the working domain if requested */ |
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if (domain == MFGPT_DOMAIN_WORKING) |
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max = 6; |
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else |
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max = MFGPT_MAX_TIMERS; |
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if (timer_nr >= max) { |
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/* programmer error. silly programmers! */ |
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WARN_ON(1); |
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goto done; |
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} |
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spin_lock_irqsave(&mfgpt->lock, flags); |
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if (timer_nr < 0) { |
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unsigned long t; |
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/* try to find any available timer */ |
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t = find_first_bit(mfgpt->avail, max); |
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/* set timer_nr to -1 if no timers available */ |
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timer_nr = t < max ? (int) t : -1; |
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} else { |
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/* check if the requested timer's available */ |
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if (!test_bit(timer_nr, mfgpt->avail)) |
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timer_nr = -1; |
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} |
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if (timer_nr >= 0) |
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/* if timer_nr is not -1, it's an available timer */ |
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__clear_bit(timer_nr, mfgpt->avail); |
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spin_unlock_irqrestore(&mfgpt->lock, flags); |
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if (timer_nr < 0) |
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goto done; |
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timer = kmalloc(sizeof(*timer), GFP_KERNEL); |
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if (!timer) { |
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/* aw hell */ |
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spin_lock_irqsave(&mfgpt->lock, flags); |
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__set_bit(timer_nr, mfgpt->avail); |
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spin_unlock_irqrestore(&mfgpt->lock, flags); |
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goto done; |
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} |
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timer->chip = mfgpt; |
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timer->nr = timer_nr; |
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dev_info(&mfgpt->pdev->dev, "registered timer %d\n", timer_nr); |
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done: |
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return timer; |
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} |
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EXPORT_SYMBOL_GPL(cs5535_mfgpt_alloc_timer); |
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/* |
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* XXX: This frees the timer memory, but never resets the actual hardware |
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* timer. The old geode_mfgpt code did this; it would be good to figure |
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* out a way to actually release the hardware timer. See comments below. |
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*/ |
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void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer) |
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{ |
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unsigned long flags; |
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uint16_t val; |
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/* timer can be made available again only if never set up */ |
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val = cs5535_mfgpt_read(timer, MFGPT_REG_SETUP); |
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if (!(val & MFGPT_SETUP_SETUP)) { |
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spin_lock_irqsave(&timer->chip->lock, flags); |
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__set_bit(timer->nr, timer->chip->avail); |
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spin_unlock_irqrestore(&timer->chip->lock, flags); |
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} |
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kfree(timer); |
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} |
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EXPORT_SYMBOL_GPL(cs5535_mfgpt_free_timer); |
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uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer, uint16_t reg) |
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{ |
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return inw(timer->chip->base + reg + (timer->nr * 8)); |
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} |
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EXPORT_SYMBOL_GPL(cs5535_mfgpt_read); |
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void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg, |
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uint16_t value) |
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{ |
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outw(value, timer->chip->base + reg + (timer->nr * 8)); |
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} |
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EXPORT_SYMBOL_GPL(cs5535_mfgpt_write); |
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/* |
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* This is a sledgehammer that resets all MFGPT timers. This is required by |
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* some broken BIOSes which leave the system in an unstable state |
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* (TinyBIOS 0.98, for example; fixed in 0.99). It's uncertain as to |
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* whether or not this secret MSR can be used to release individual timers. |
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* Jordan tells me that he and Mitch once played w/ it, but it's unclear |
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* what the results of that were (and they experienced some instability). |
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*/ |
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static void reset_all_timers(void) |
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{ |
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uint32_t val, dummy; |
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/* The following undocumented bit resets the MFGPT timers */ |
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val = 0xFF; dummy = 0; |
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wrmsr(MSR_MFGPT_SETUP, val, dummy); |
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} |
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/* |
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* This is another sledgehammer to reset all MFGPT timers. |
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* Instead of using the undocumented bit method it clears |
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* IRQ, NMI and RESET settings. |
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*/ |
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static void soft_reset(void) |
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{ |
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int i; |
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struct cs5535_mfgpt_timer t; |
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for (i = 0; i < MFGPT_MAX_TIMERS; i++) { |
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t.nr = i; |
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cs5535_mfgpt_toggle_event(&t, MFGPT_CMP1, MFGPT_EVENT_RESET, 0); |
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cs5535_mfgpt_toggle_event(&t, MFGPT_CMP2, MFGPT_EVENT_RESET, 0); |
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cs5535_mfgpt_toggle_event(&t, MFGPT_CMP1, MFGPT_EVENT_NMI, 0); |
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cs5535_mfgpt_toggle_event(&t, MFGPT_CMP2, MFGPT_EVENT_NMI, 0); |
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cs5535_mfgpt_toggle_event(&t, MFGPT_CMP1, MFGPT_EVENT_IRQ, 0); |
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cs5535_mfgpt_toggle_event(&t, MFGPT_CMP2, MFGPT_EVENT_IRQ, 0); |
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} |
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} |
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/* |
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* Check whether any MFGPTs are available for the kernel to use. In most |
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* cases, firmware that uses AMD's VSA code will claim all timers during |
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* bootup; we certainly don't want to take them if they're already in use. |
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* In other cases (such as with VSAless OpenFirmware), the system firmware |
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* leaves timers available for us to use. |
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*/ |
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static int scan_timers(struct cs5535_mfgpt_chip *mfgpt) |
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{ |
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struct cs5535_mfgpt_timer timer = { .chip = mfgpt }; |
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unsigned long flags; |
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int timers = 0; |
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uint16_t val; |
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int i; |
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/* bios workaround */ |
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if (mfgpt_reset_timers == 1) |
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reset_all_timers(); |
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else if (mfgpt_reset_timers == 2) |
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soft_reset(); |
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/* just to be safe, protect this section w/ lock */ |
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spin_lock_irqsave(&mfgpt->lock, flags); |
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for (i = 0; i < MFGPT_MAX_TIMERS; i++) { |
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timer.nr = i; |
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val = cs5535_mfgpt_read(&timer, MFGPT_REG_SETUP); |
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if (!(val & MFGPT_SETUP_SETUP) || mfgpt_reset_timers == 2) { |
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__set_bit(i, mfgpt->avail); |
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timers++; |
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} |
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} |
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spin_unlock_irqrestore(&mfgpt->lock, flags); |
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return timers; |
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} |
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static int cs5535_mfgpt_probe(struct platform_device *pdev) |
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{ |
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struct resource *res; |
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int err = -EIO, t; |
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if (mfgpt_reset_timers < 0 || mfgpt_reset_timers > 2) { |
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dev_err(&pdev->dev, "Bad mfgpt_reset_timers value: %i\n", |
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mfgpt_reset_timers); |
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goto done; |
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} |
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/* There are two ways to get the MFGPT base address; one is by |
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* fetching it from MSR_LBAR_MFGPT, the other is by reading the |
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* PCI BAR info. The latter method is easier (especially across |
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* different architectures), so we'll stick with that for now. If |
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* it turns out to be unreliable in the face of crappy BIOSes, we |
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* can always go back to using MSRs.. */ |
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res = platform_get_resource(pdev, IORESOURCE_IO, 0); |
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if (!res) { |
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dev_err(&pdev->dev, "can't fetch device resource info\n"); |
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goto done; |
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} |
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if (!request_region(res->start, resource_size(res), pdev->name)) { |
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dev_err(&pdev->dev, "can't request region\n"); |
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goto done; |
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} |
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/* set up the driver-specific struct */ |
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cs5535_mfgpt_chip.base = res->start; |
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cs5535_mfgpt_chip.pdev = pdev; |
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spin_lock_init(&cs5535_mfgpt_chip.lock); |
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dev_info(&pdev->dev, "reserved resource region %pR\n", res); |
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/* detect the available timers */ |
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t = scan_timers(&cs5535_mfgpt_chip); |
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dev_info(&pdev->dev, "%d MFGPT timers available\n", t); |
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cs5535_mfgpt_chip.initialized = 1; |
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return 0; |
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done: |
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return err; |
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} |
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static struct platform_driver cs5535_mfgpt_driver = { |
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.driver = { |
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.name = DRV_NAME, |
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}, |
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.probe = cs5535_mfgpt_probe, |
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}; |
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static int __init cs5535_mfgpt_init(void) |
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{ |
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return platform_driver_register(&cs5535_mfgpt_driver); |
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} |
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module_init(cs5535_mfgpt_init); |
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MODULE_AUTHOR("Andres Salomon <[email protected]>"); |
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MODULE_DESCRIPTION("CS5535/CS5536 MFGPT timer driver"); |
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MODULE_LICENSE("GPL"); |
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MODULE_ALIAS("platform:" DRV_NAME);
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